Intel Corporation

Infineon Technologies Ag

Google Inc.

Sony Corporation

Sony Group Corporation

Annalisa Cappellani

Kelin J Kuhn

Rafael Rios

Stephen M Cea

Seiyon Kim

Tahir Ghani

Martin D Giles

Harry Gomez

Abhijit Jayant Pethe

Glenn A Glass

Titash Rakshit

Jack T Kavalieros

Willy Rachmady

Peter Chang

Robert S Chau

Matthew V Metz

Van H Le

Mark L Doczy

Suman Datta

Justin K Brask

Chris E Barns

Anand S Murthy

Mark T Bohr

Clair C Webb

Uday Shah

Aaron D Lilak

Cory E Weber

Peter G Tolchinsky

Patrick H Keys

Bruce E Beattie

Aaron A Budrevich

Pragyansri Pathi

Sivakumar Mudanai

Mayank Sahni

Sanaz Kabehie Gardner

Matthias Goldbach

Rudolf Lachner

Gopinath Bhimarasetti

Kuan-Yueh Shen

Dirk Schumann

Ludwig Dittmar

Sanaz Kabehie

Aura Cecilia Davila Latorre

Clair Webb

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

Gate contact structure over active gate and method to fabricate same

Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Silicon and silicon germanium nanowire structures

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Nanowire structures having non-discrete source and drain regions

Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.

Gate-all-around (GAA) transistors with nanowires on an isolation pedestal

Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

Semiconductor device having metallic source and drain regions

Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.

Semiconductor devices having modulated nanowire counts

Gate-all-around (GAA) transistor with stacked nanowires on locally isolated substrate

Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

CMOS nanowire structure

Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

Semiconductor device with isolated body portion

Growing community of inventors

Portland, OR, United States of America

Annalisa Cappellani