Calypto Design Systems, Inc.

Cadence Design Systems, Inc.

Mentor Graphics Corporation

Calypto Designs Systems

Anmol Mathur

Venky Ramachandran

Sumit Roy

Nikhil Tripathi

Malay Haldar

Deepak Goyal

Sanjeev Saluja

Pankaj P Chauhan

Mohit Kumar

Gagan Hasteer

Abhishek Roy

Rajarshi Mukherjee

Nikhil Sharma

Shail Bains

Abhishek Ranjan

A system, method and computer program product are provided for conditionally eliminating a memory read request. In use, a memory read request is identified. Additionally, it is determined whether the memory read request is an unnecessary memory read request. Further, the memory read request is conditionally eliminated, based on the determination.

System, method, and computer program product for conditionally eliminating a memory read request

A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, the transformation identifies a word-level functionality of the at least some of the finite portions by converting bit-level functionality into word-level functionality.

System, method, and computer program product for determining equivalence of netlists utilizing at least one transformation

A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, an abstraction is performed on the netlist.

System, method, and computer program product for determining equivalence of netlists utilizing abstractions and transformations

An integrated circuit design system, method, and computer program product are provided that takes into account signal stability. In use, at least one condition is identified where an output of a logic element before receipt of a clock signal is the same as the output of the logic element after receipt of the clock signal. To this end, such logic element may be disabled based on the identified condition for power savings or other purposes.

Integrated circuit design system, method, and computer program product that takes into account the stability of various design signals

An integrated circuit design system, method, and computer program product are provided that takes into account observability based clock gating conditions. In use, at least one condition is identified where an output of a first logic element is not a function of a first input of the first logic element, due to a second input of the first logic element. To this end, at least one second logic element may be disabled based on the identified condition for power savings or other purposes.

Integrated circuit design system, method, and computer program product that takes into account observability based clock gating conditions

A mapping system, method and computer program product are provided. In use, at least one arithmetic operator is received. Further, the at least one arithmetic operator is mapped to at least one cell, at a word-level.

System, method and computer program product for word-level operator-to-cell mapping

A system, method and computer program product are provided for equivalency checking between a first design and a second design having sequential differences. To accomplish the equivalency checking, sequential differences between a first design and a second design are identified. It is then determined whether the first design and the second design are equivalent, utilizing the identified sequential differences.

System, method and computer program product for equivalence checking between designs with sequential differences

A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.

Method and system for inplace symbolic simulation over multiple cycles of a multi-clock domain design

The present invention discloses a method and system for computer-aided circuit design for checking the equivalence of data flow graphs by splitting data flow graphs representing finite precision arithmetic circuits into lossless subgraphs representing infinite-precision arithmetic circuits, and edges with information loss. The set of lossless subgraphs generated are leveled, and checked for equivalence as expressions. The edges with information loss are compared by establishing the equivalence of their bit width. The present invention declares data flow graphs as equal, if the respective lossless subgraphs and the bit-width at the corresponding edges with information loss are equal.

Circuit comparison by information loss matching

A Huffman algorithm is applied to revise the topology of a data flow graph. The result of the application of the algorithm is an increase in the sizes of at least some clusters (i.e., enhanced mergeability). The Huffman rebalancing of the topology may also result in the benefit of allowing further pruning of the bitwidths of data flow paths, which may further enhance mergeability. Thus, the algorithm may be applied with a maximum information content analysis.

Reducing datapath widths by rebalancing data flow topology

Required precision and information content of datapath signals are used to define functionally safe transformations on data flow graphs. These transformations reduce widths of datapath operators and edges and enhance the mergeability of operators. An algorithm for optimally balancing data flow graph topology to further reduce the data path widths and further enhance mergeability is combined with the above in an iterative algorithm for optimizing DFGs.

Procedure for optimizing mergeability and datapath widths of data flow graphs

A practical definition for determining a required precision is provided and used to reduce the widths of operators and edges of data flow graphs. A bottom-up procedure for systematically pruning data flow graphs is described. The result is shown to enhance the mergeability of subgraphs and provide reduced data path widths. This may result in lower area, power requirements and other benefits as readily understood in the field of circuit design.

Enhancing mergeability of datapaths and reducing datapath widths responsively to required precision

A practical definition for determining an upper bound on information content is provided and used to reduce the widths of operators and edges of data flow graphs. A top down procedure for systematically pruning data flow graphs is described. The result is shown to enhance the mergeability of subgraphs and provide reduced data path widths. This may result in lower area, power requirements and other benefits as readily understood in the field of circuit design.

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San Jose, CA, United States of America

Anmol Mathur