International Business Machines Corporation

Novellus Systems Incorporated

Samsung Electronics Co., Ltd.

Applied Materials, Inc.

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Anita Madan

Kwong Hon Wong

Nancy R Klymko

Keith Kwong Hon Wong

Xiao Hu Liu

Conal Eugene Murray

Richard Anthony Conti

Ashima B Chakravarti

Chung Woh Lai

Daewon Yang

J Campbell Scott

Kriteshwar Kaur Kohli

Teresa L Pinto

Roy H Tilghman

Klaus W Schwarz

Ronald P Bourque

Michael C Smits

Zhijiong Luo

Thomas N Adam

Nivo Rovedo

Oh-Jung Kwon

Robert J Purtell

Yaocheng Liu

Jinghong Li

Eric C Harley

Woo-Hyeong Lee

Donghun Kang

Bruce Bennett Doris

Stephen W Bedell

Oleg Gluschenkov

Judson Robert Holt

Sanjay C Mehta

Shyng-Tsong Chen

Anil Kumar Chinthakindi

Jin Ping Liu

Kenneth Jay Stein

John Campbell Scott

Michael Abramovich Gribelyuk

Patrick William Dehaven

Sadanand Vinayak Deshpande

Steven E Molis

Richard J Murphy

Patrick Edward Lindo

Jun-Keun Kwak

Ramaseshan Suryanarayanan Iyer

Romany Ghali

Gregory Wayne Dibello

Klaus Schwarz

Jinghong H Li

A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.

Capacitance monitoring using x-ray diffraction

Capacitance monitoring using X-ray diffraction

Evaluating a semiconductor wafer may include recording a first intensity of a reflection of an X-ray beam onto a test area on a substrate of the semiconductor wafer at a detector as the X-ray beam is projected substantially perpendicular to a length of expected, periodic structures in the test area and at an angle defined between the X-ray beam and a surface of the test area. Second intensities may be recorded of the reflection of the X-ray beam onto the test area as the X-ray beam is projected onto the test area at increments from the angle. Intensity peaks in the recordings of the first and second intensities are identified and, based on positions of the intensity peaks relative to the test area, a peak spacing between the plurality of expected, periodic structures is determined indicative of pitch walking or epitaxial merge.

Evaluating semiconductor wafers for pitch walking and/or epitaxial merge

A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.

Dislocation engineering using a scanned laser

A method for manipulating dislocations from a semiconductor device includes directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of the semiconductor device and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam. Manipulating the plurality of dislocations includes directly scanning the plurality of dislocations with the light-emitting beam to manipulate a location of each of the plurality of dislocations on the surface portion of the semiconductor body by adjusting a temperature of the surface portion of the semiconductor body corresponding to the plurality of dislocations and adjusting a scan speed of the a light-emitting beam.

A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices.

Measurement of CMOS device channel strain by X-ray diffraction

A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.

An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Integrated circuit system with carbon and non-carbon silicon

When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method of repairing process induced dielectric damage from forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes treating an exposed area of the ILD material to create a carbon-rich area, and metallizing the carbon-rich area. One embodiment includes providing treatment to an exposed sidewall area of the ILD material to create a carbon-rich area by irradiating the exposed area using a gas cluster ion beam (GCIB) generated through a gas including a straight chain or branched, aliphatic or aromatic hydrocarbon, and metallizing the carbon-rich area.

Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species

A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 &#x212b;.

Method of forming nitride films with high compressive stress for improved PFET device performance

In a method for use of x-ray diffraction to measure the strain on the top silicon germanium layer of an SOI substrate, the location of the peak diffraction area of an upper silicon layer of the SOI substrate is determined by first determining the peak diffraction area of the upper silicon layer on a reference pad (where the SOI thickness is about 700-900 Angstroms) within a die formed on a semiconductor wafer. The x-ray beam then moves to that location on the pad of interest to be measured and begins the XRD scan on the pad of interest to ultimately determine the strain of the top silicon germanium layer of the pad of interest.

Measuring strain of epitaxial films using micro x-ray diffraction for in-line metrology

A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400&#xb0; C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over the wafer following transfer of the wafer from the degas chamber to the deposition chamber, and annealing the semiconductor wafer so as to create silicide regions at portions on the wafer where nickel material is formed over silicon.

Method for improved formation of nickel silicide contacts in semiconductor devices

A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at a temperature of about 400&#xb0; C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a cobalt layer over the wafer at a point in time when the semiconductor wafer has cooled to temperature range of about 275-300&#xb0; C., depositing a cap layer over the cobalt layer, and annealing the semiconductor wafer so as to create silicide contacts at portions on the wafer where cobalt is formed over silicon.

Method for improved formation of cobalt silicide contacts in semiconductor devices

The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

N-channel MOSFETs comprising dual stressors, and methods for forming the same

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Danbury, CT, United States of America

Anita Madan