Micron Technology Incorporated

Intel Corporation

Anish A Khandekar

Kunal Shrotri

Jeffery B Hull

Hung-Wei Liu

John David Hopkins

Gordon A Haller

Tom Jibu John

Fei Wang

Jie Li

Dimitrios Pavlopoulos

Sameer Chhajed

Zhiqiang Xie

David H Wells

Justin B Dorhout

Aaron R Wilson

Darwin Franseda Fan

Shen Hu

Derek F Lundberg

Charles H Dennison

Hongbin Zhu

Ashonita A Chavan

Vassil N Antonov

Irina V Vasilyeva

Brett D Lowe

Manuj Nahar

Christopher J Larsen

Brian J Cleereman

Albert Liao

Nicholas R Tapias

Masihhur R Laskar

Xue-Feng Lin

Lining He

Kunal R Parekh

Yongjun Jeff Hu

Luan C Tran

Chris M Carlson

Nancy M Lomeli

Mark W Kiehlbauch

Collin Howder

Sanjeev Sapra

Niraj B Rana

Alex J Schrinsky

Silvia Borsari

Yi Fang Lee

Ryan L Meyer

Lequn Jennifer Liu

Zhixin Xu

Duo Mao

Ee Ee Eng

Dong Liang

Greg Light

Pavan Aella

Thomas Arthur Figura

Shyam Surthi

Adam William Saxler

Matthew J King

Xiao Li

Lars P Heineck

Erik R Byers

Guangjun Yang

Jerome A Imonigie

Andrew Li

Diem Thy N Tran

Wei Yeeng Ng

Ervin T Hill

Yoshitaka Nakamura

Sau Ha Cheung

Corey Staller

Jixin Yu

Somik Mukherjee

Jeffrey B Hull

Ning Lu

Jeffery Brandt Hull

Sateesh Koka

A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

Vertical transistor, integrated circuitry, method of forming a vertical transistor, and method of forming integrated circuitry

Methods, apparatuses, and systems related to forming a semiconductor using hybrid oxidation are described. An example method includes forming an opening to create an isolation region in a semiconductor substrate. The example method further includes depositing a first dielectric into the isolation region at a first oxidation rate. The example method further includes depositing a second dielectric into the isolation region at a second oxidation rate.

Semiconductor formation using hybrid oxidation

Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

On-die formation of single-crystal semiconductor structures

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μmof one another. Other embodiments, including methods, are disclosed.

Transistor and methods of forming integrated circuitry

Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rwhich is the mean peak-to-valley distance along the undulating topography. The Ris at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having rugged material fill, and methods of forming integrated assemblies

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 &#x3bc;mof one another. Other embodiments, including methods, are disclosed.

A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.

Vertical transistors

A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon

A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells

Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

Semiconductor structure formation

Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.

Semiconductor contact formation

An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.

Growing community of inventors

Boise, ID, United States of America

Anish A Khandekar