Freescale Semiconductor,inc.

Nxp USA, Inc.

Anis Mahmoud Jarrar

David Russell Tipple

Colin MacDonald

Stefano Pietri

Mark Douglas Hall

Alexander Hoefler

Chris C Dao

Juxiang Ren

LeRoy Winemberg

Nancy Hing-Che Amedeo

Steven K Watkins

Dat Tat Tran

John Mark Boyer

Jim C Nash

John M Dalbey

William C Moyer

Anirban Roy

Hector Adrian Sanchez

Frank Kelsey Baker, Jr

Savithri Sundareswaran

Mikhail Yurievich Semenov

Alistair James Gorman

Kristen L Mason

Rishi Bhooshan

Viacheslav Sergeyevich Kalashnikov

Nisar Ahmed

Surya Veeraraghavan

Anuj Singhania

Shilpa Gupta

Xiaoxiao Wang

Jorge Arturo Corso

John F West

Jeff L Warner

Emmanuel Chukwuma Onyema

Benjamin S Huang

Jifeng Chen

Bryan T Weston

Hadi Ahmadi Balef

Balaji Rajasekaran

Saji George

A margin sensing circuit coupled to a flip flop of a critical data path includes a delay generator, a selector circuit which selects a delayed data output from the delay generator, a shadow latch corresponding to the flip flop, a comparator circuit which provides a match error indicator based on a comparison between a latched data output from the flip flop and a latched shadow output from the shadow latch, and an error latch to provide an error indicator based on the match error indicator. A correcting circuit includes a clock delay generator configured to receive a clock and provide a plurality of delayed clocks, and a clock selector circuit to select a delayed clock of the plurality of delayed clocks based on a set of clock select signals, in which each of the flip flop and the shadow latch are clocked by the selected delayed clock.

Integrated circuit with timing correction circuitry

A critical data path of an integrated circuit includes a flip flop configured to receive a data input and provide a latched data output. A monitoring circuit includes a delay generator configured to receive the data input and provide a plurality of delayed data outputs corresponding to delayed versions of the data input with increasing amounts of delay, a selector circuit configured to select one of the plurality of delayed outputs based on a programmable control value, and a shadow latch coupled to an output of the selector circuit and configured to latch a value at its input to provide as a latched shadow output. A comparator circuit provides a match error indicator based on a comparison between the first latched data output and the latched shadow output, and an error indicator is provided which indicates whether or not an impending failure of the critical data path is detected.

Integrated circuit having an in-situ circuit for detecting an impending circuit failure

An integrated circuit includes a master-slave storage element having a data input coupled to receive a data signal and an asymmetrical clock generator coupled to provide an asymmetrical clock signal to the master-slave storage element. A first phase of the asymmetrical clock signal is configured for inhibiting intermediate data signal transitions from propagating through the master portion of the master-slave storage element.

Duty cycle control for reduced dynamic power consumption

An integrated circuit includes a pulse generator having at least one delay circuit with an input that receives a clock signal and an output that provides a delayed clock pulse. The delayed clock pulse has a width proportional to an amount of time required to maintain a magnitude of the clock signal. A pulse latch circuit includes a clock input coupled to receive the delayed clock pulse, a data input coupled to receive a data value, and a data output, wherein the pulse latch circuit outputs and holds the data value at the data output each time the delayed clock pulse is provided at the clock input, and the pulse latch circuit operates on a continuous voltage source that supplies power during power on and power off modes.

Pulsed latch system with state retention and method of operation

A processing system tags read and write transaction packets that are functionally safe and suppresses redundant processing and error checking for functionally safe tagged transaction packets. The processing system includes compute elements that are interconnected via an interconnect fabric that includes resources to route operations. The interconnect fabric includes redundant resources to execute the same routing operations and comparator elements to indicate an error in response to detecting a mismatch between the output of a resource and its corresponding duplicate resource. The interconnect fabric selectively activates the duplicate resources and comparator elements in response to a tag associated with a transaction packet indicating that the transaction packet is safety-critical.

Dynamic suppression of error detection in processor switch fabric

A semiconductor apparatus includes a first device cell and a second device cell. The first device cell includes a first active region including a first set of device fins, an insulator layer disposed over the first set of device fins, a first gate fin over the first set of fins, and a first edge fin disposed over a first edge of the first active region. The second device cell is adjacent the first device cell and includes a second active region including a second set of device fins, the insulator layer disposed over the second set of device fins, a second gate fin over the second set of device fins, and a second edge fin disposed over a second edge of the second active region. The first edge fin and the second edge fin are connected to a power rail, a ground rail, or to each other to define a capacitor between the first device cell and the second device cell.

Decoupling capacitors using regularity finFET structures and methods for making same

A software update architecture, system, apparatus, and methodology are provided for performing block-based swapping of OTA software stored as a plurality of compressed blocks in a first, smaller NVM with the system software stored as a plurality of decompressed blocks in a second, larger NVM by using a first decompressor circuit and first scratch memory to sequentially decompress each compressed code block of OTA software for storage in decompressed form as updated system software in the second, larger NVM while using a first compressor circuit and second scratch memory to sequentially compress each decompressed code block of system software for storage in compressed form as backup system software in the first, smaller NVM.

NVM architecture with OTA support

A FinFet capacitor structure includes a first, second, third, and fourth FinFet fin, a contiguous gate layer over the fins, first and second source/drain contacts in direct physical contact with the first FinFet fin on either side of the gate layer, a first gate contact in direct physical contact with a portion of the contiguous gate layer directly over the second FinFet fin, third and fourth source/drain contacts in direct physical contact with the third FinFet fin on either side of the gate layer, and a second gate contact in direct physical contact with a portion of the contiguous gate layer directly over the fourth FinFet fin. The first, second, third, and fourth source/drain contacts are all connected to a first power supply rail, and the first and second gate contacts are all connected to a second power supply rail.

Fin field-effect transistor (FinFet) capacitor structure for use in integrated circuits

A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.

High capacity I/O (input/output) cells

An integrated circuit includes a clock generator to generate a first clock signal, a delay circuit to generate a second clock signal as a delayed version of the first clock signal, and a plurality of series-connected delay elements having a plurality of outputs, wherein each output from an initial output to a last output is configured to provide the second clock signal delayed by an increasing number of series-connected delay elements. The circuit includes a plurality of flip-flops, wherein a first input of each flip flop is coupled to receive the first clock signal and a second input of each flip flop from an initial flip-flop to a last flip-flop is coupled to receive a corresponding output of the series-connected delay elements from the initial output to the last output, respectively. The circuit includes a plurality of sticky flops, each corresponding to a flip-flop of the plurality of flip-flops.

Power supply noise sensor

An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.

Integrated circuit with power saving feature

A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.

Systems and methods for reducing power consumption in semiconductor devices

A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Low swing flip-flop with reduced leakage slave latch

A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor.

Supply voltage regulation with temperature scaling

A CMOS cell incorporated on an integrated circuit including a PMOS transistor and an NMOS transistor. The current terminals of the PMOS and NMOS transistors are coupled in series between a lower voltage supply rail and a reference rail. The well connection of the PMOS transistor is coupled to an upper voltage supply rail having a voltage level greater than the lower voltage supply rail. The CMOS cell has low voltage swing and low leakage current to reduce power consumption. A second PMOS and NMOS transistor pair may be included and coupled in similar manner and to the first PMOS and NMOS pair to form a non-inverting cell. The PMOS transistors may be implemented in an N-well that is conductively tied to the upper supply voltage rail to avoid isolation barriers. The cell may be used in a clock tree to significantly reduce power consumption of the integrated circuit.

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Austin, TX, United States of America

Anis Mahmoud Jarrar