International Business Machines Corporation

Globalfoundries Inc.

Anirban Basu

Amlan Majumdar

Guy M Cohen

Davood Shahrjerdi

Bahman Hekmatshoartabari

Jeffrey W Sleight

Pouya Hashemi

Kuen-Ting Shiu

Yu Zhu

Ali Khakifirooz

Wilfried Haensch

Yanning Sun

Dimitri Kanevsky

Tara N Sainath

Cheng-Wei Cheng

Aleksandr Y Aravkin

Devendra K Sadana

Stephen W Bedell

Cyril Cabral, Jr

Uzma B Rana

Ryan M Martin

Premal Y Shah

A structure includes a semiconductor substrate, a buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer.

Device isolation using preferential oxidation of the bulk substrate

A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.

Multi-junction solar cell

A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.

A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

Charge carrier transport facilitated by strain

Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

Device isolation for III-V substrates

A method includes providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer, etching the semiconductor layer so as to form a fin and exposing the buffer layer, etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed, and oxidizing the buffer layer and fin so as to form an oxide layer under the fin.

A structure includes a semiconductor substrate, a semiconductor buffer layer disposed on the semiconductor substrate, an oxide layer disposed on the buffer layer, and a fin including a semiconductor material disposed on the oxide layer. The fin and the buffer layer are epitaxially aligned to the semiconductor substrate.

Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

Silicon-containing, tunneling field-effect transistor including III-N source

A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench.

Fabrication process for mitigating external resistance of a multigate device

A structure and method for forming a substrate, a buffer layer disposed on the substrate, an oxide layer disposed on the buffer layer, and a fin comprising a semiconductor material disposed on the oxide layer.

Systems and methods for generating a tactile representation of an object are provided. A method for generating a tactile representation of an object, comprises obtaining a microscopic image of a surface of the object, processing data corresponding to the image to generate a roughness pattern for the object based on the image, calibrating the roughness pattern with a predetermined material, and simulating the roughness pattern on an electronic device.

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Elmsford, NY, United States of America

Anirban Basu