Texas Instruments Corporation

National Semiconductor Corporation

Anindya Poddar

Hau Thanh Nguyen

Ashok S Prabhu

Woochan Kim

Luu Thanh Nguyen

Vivek Kishorechand Arora

Kengo Aoya

Masamitsu Matsuura

Mutsumi Masumoto

Jaime A Bayan

Yi Yan

Rajeev Dinkar Joshi

Makoto Shibuya

Ken Pham

Makoto Yoshino

Vijaylaxmi Gumaste Khanolkar

Mahmud Halim Chowdhury

Randall Walberg

Dibyajat Mishra

Sreenivasan Kalyani Koduri

Thomas Dyer Bonifield

Yogesh Kumar Ramadass

Jeffrey Anthony Morroni

Kurt Peter Wachtler

Nghia Thuc Tu

Sujan Kundapur Manohar

Genki Yano

Will Kiang Wong

Usman Mahmood Chaudhry

Shoichi Iriguchi

Hiroyuki Sada

Chetan Paydenkar

Hideaki Matsunaga

Tomoko Noguchi

Swaminathan Sankaran

Peter B Johnson

Nikhil Vishwanath Kelkar

Tao Feng

John Paul Tellkamp

Giovanni Frattini

Ting-Ta Yen

Hassan Omar Ali

Shaw Wei Lee

Roberto Giampiero Massolini

Honglin Guo

Venkatesh Srinivasan

David Chin

Daiki Komatsu

Artur Darbinyan

Joe Adam Garcia

Jie Mao

Vijaylaxmi Gumaste

Thanh Lequang

Ming Li

Amin Ahmad Sijelmassi

Lianxi Shen

Ka Heng The

Ram Veeraraghavan

Edgar Dorotyao Balidoy

Murali Kittappa

Kurt Edward Sincerbox

Masamitsu Matasuura

Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

High voltage flip-chip on lead (FOL) package

In a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.

Microelectronic device package with integral antenna module and semiconductor device

In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.

Conductive members atop semiconductor packages

In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.

Metal ribs in electromechanical devices

In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

Frame design in embedded die package

Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

Embedded die packaging with integrated ceramic substrate

In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

Package for stress sensitive component and semiconductor device

In accordance with an embodiment of the application a method of forming an integrated magnetic device is described. A prepreg or core is mounted on a carrier. A winding layer is plated and patterned on the prepreg or core. Vias are plated. The silicon is placed on a die attach pad, ensuring sufficient clearance of die to vias and d/a char. The assembly is laminated and grinded to expose the vias. A 2layer of vias is provided by sputtering or plating followed by laminating assembly; and grinding assembly to expose vias. The windings are plated and patterned. A solder mask (SMSK) is applied and assembly finished.

Forming integrated inductors and transformers with embedded magnetic cores

A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

Semiconductor device package with thermal pad

In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

Packages with electrical fuses

In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

Flip chip packaged devices with thermal pad

A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.

Semiconductor package having an interdigitated mold arrangement

A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

Semiconductor package with isolated heat spreader

Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

Electronic package for integrated circuits and related methods

Growing community of inventors

Sunnyvale, CA, United States of America

Anindya Poddar