Texas Instruments Corporation

Qualcomm Incorporated

Angelo Pinto

Gregory Eric Howard

Jeffrey A Babcock

Scott G Balster

Alfred Haeusler

Rick L Wise

Weize W Xiong

Scott Balster

Cloves Rinn Cleavelin

Christoph Dirnecker

Michael Schober

Shaofeng Yu

Frank Scott Johnson

Philipp Steinmann

Benjamin P McKee

Phillipp Steinmann

Jeffrey Babcock

Periannan Chidambaram

Manfred Schiekofer

Haowen Bu

Badih El-Kareh

Ajith Varghese

Manfred Ramin

Manuel A Quevedo-Lopez

Alfred Hausler

Ricardo A Romani

Sidharth Rastogi

Luca Mattii

Ranganayakulu Konduri

Gerard Patrick Baldwin

Routing layers, e.g., back-end of line (BEOL) routing layers, of a semiconductor device are disclosed. Unlike conventional routing layers, the proposed routing layers include mixed pitch track patterns. As such, routing layers with reduced resistance-capacitance (RC) and low routing cost may be achieved.

Mixed pitch track pattern

Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orienations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0&#xb0; or 90&#xb0; rotations.

Integrated circuits with aligned (100) NMOS and (110) PMOS finFET sidewall channels

An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0&#xb0; or 90&#xb0; rotations.

Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels

A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer () beneath the gate dielectric () and source and drain regions () of a MOS transistor. The carbon containing layer () will prevent the diffusion of dopants into the region () directly beneath the gate dielectric layer ().

Advanced CMOS using super steep retrograde wells

An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having () crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having () crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0&#xb0; or 90&#xb0; rotations.

An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (), each having a buried collector region ('). A carbon-bearing diffusion barrier () is disposed over the buried collector region (&#x2032;), to inhibit the diffusion of dopant from the buried collector region (&#x2032;) into the overlying epitaxial layer (). The diffusion barrier () may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks () may be used to define the locations of the buried collector regions (&#x2032;) that are to receive the carbon; for example, portions underlying eventual collector contacts () may be masked from the carbon implant so that dopant from the buried collector region (&#x2032;) can diffuse upward to meet the contact (). MOS transistors () including the diffusion barrier () are also disclosed.

Control of dopant diffusion from buried layers in bipolar integrated circuits

A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0&#xb0; or 90&#xb0; rotations.

Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels

A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.

Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate

A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon.

Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow

Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.

Integration scheme for reducing border region morphology in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin includes a channel of a first surface of a first crystal orientation. A NMOS fin of another MuGFET is formed on the substrate. The NMOS fin includes a channel on the substrate at one of 0&#xb0; and 90&#xb0; to the PMOS fin and includes a second surface of a second crystal orientation.

Growing community of inventors

San Diego, CA, United States of America

Angelo Pinto