Tokyo Electron Limited

Tokyo Electron Limi Ted

Angelique Denise Raley

Katie Lutker-Lee

Akiteru Ko

Nihar Mohanty

Yen-Tien Lu

Andrew W Metz

Xinghua Sun

David L O'Meara

Subhadeep Kal

Aelan Mosden

Eric Chih-Fang Liu

Junling Sun

Scott W Lefevre

Jeffrey Smith

Robert Daniel Clark

Kandabara N Tapily

Sophie Thibaut

Alok Ranjan

Kai-Hung Yu

Qiang Zhao

Richard Farrell

Lior Huli

Nicholas Joy

Shan Hu

Henan Zhang

Shihsheng Chang

Kiyohito Ito

Christopher Cole

Qiaowei Lou

Gerrit J Leusink

Joe Lee

Takuya Mori

Jeffrey C Shearer

Cory Wajda

Toshio Hasegawa

Kaoru Maekawa

Hiroto Ohtake

Mingmei Wang

Soo Doo Chae

Yu-Hao Tsai

Yoshihiro Kato

Hirokazu Aizawa

Hiroyuki Suzuki

Dina Triyoso

Ya-Ming Chen

Elliott Franke

Satoru Nakamura

Michael Edley

Jake Kaminsky

Stephanie Oyola-Reynoso

Kal Subhadeep

Choong-man Lee

A method of forming a semiconductor device includes receiving a substrate in a plasma chamber, the substrate comprising an EUV patterned first mask material comprising a metal-based resist (MBR) and an underlying layer disposed between the substrate and the first mask material; depositing, selectively, a second mask material on the first masking layer using a first plasma comprising a source gas that reacts selectively with the first masking layer relative to the underlying layer; and etching the portion of the underlying layer to form a patterned underlying layer using the second masking layer and the first masking layer as an etch mask.

Patterning features with metal based resists

A method of processing a substrate that includes: etching a recess in the substrate using a metal hard mask (MHM) layer as an etch mask, the substrate including a dielectric layer over a conductive layer the includes a first conductive material, a portion of the MHM layer remaining over top surfaces of the dielectric layer after the etching; depositing a sacrificial fill over the substrate to at least partially fill the recess; removing the remaining portion of the MHM layer to expose the top surfaces while protecting the recess with the sacrificial fill; removing the sacrificial fill from the recess after removing the MHM layer, the removing of the sacrificial fill including exposing a portion of the conductive layer; and depositing a second conductive material to fill the recess, the depositing of the second conductive material providing an electrical connection between the conductive layer and the second conductive material.

Metal hard mask integration

A method for patterning a substrate includes: forming a first photoresist etch mask with an extreme ultraviolet (EUV) lithography process, the first photoresist etch mask including first through openings, the first photoresist etch mask including a metal-based photoresist material; forming a second photoresist etch mask over the first photoresist etch mask, the second photoresist etch mask including second through openings; and forming first openings, through the first and the second photoresist etch masks, in a region of the substrate that vertically overlaps both the first through openings and the second through openings.

Method for patterning a substrate using photolithography

A method of processing a substrate that includes: forming a first plurality of lines and a first plurality of recesses, each of the plurality of lines being separated from an adjacent one of the plurality of lines by one of the plurality of recesses, the first plurality of lines including a first material and formed over a to-be-patterned layer; performing a cyclic process including: depositing a mask material over the first plurality of lines and within the first plurality of recesses, the mask material deposited defining a second plurality of lines, each of the second plurality of lines dividing one of the first plurality of recesses to form a second plurality of recesses; and performing a trimming process to increase critical dimensions of the second plurality of recesses; and patterning the to-be-patterned layer using the first plurality of lines and the second plurality of lines as an etch mask.

Pitch scaling in microfabrication

A method of processing a substrate that includes: exposing a substrate to a first plasma including carbon, the substrate including a first layer including a dielectric material and a second layer including a metal, the first plasma forming a first carbonaceous deposit over the first layer and a second carbonaceous deposit over the second layer; exposing the first carbonaceous deposit and the second carbonaceous deposit to a second plasma including halogen, the second plasma selectively etching the second carbonaceous deposit relative to the first carbonaceous deposit to expose a surface of the second layer; and exposing the first carbonaceous deposit and the exposed surface of the second layer to the second plasma to selectively etch the second layer relative to the first carbonaceous deposit, the first carbonaceous deposit protecting the first layer from being etched by the second plasma.

Pre-etch treatment for metal etch

A method of processing a substrate that includes: depositing a photoactive metal-based hard mask (photo-MHM) over an underlying layer, the underlying layer formed over a substrate, the photo-MHM including a metal; depositing a dielectric over the photo-MHM; etching a portion of the dielectric to form a first feature; depositing a spacer material over the first feature; etching the spacer material to expose top surfaces of the dielectric and a first portion of the photo-MHM; exposing the photo-MHM to a first ultraviolet light (UV) radiation through a first photomask, a first unmasked region of the photo-MHM being photoreacted due to the exposure to the first UV radiation; after the exposure, developing the photo-MHM to form a second feature in the photo-MHM; and etching the underlying layer using the photo-MHM as an etch mask.

Photoactive metal-based hard mask integration

Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

Methods for forming self-aligned contacts using spin-on silicon carbide

Methods are provided herein for forming spacers on a patterned substrate. A self-aligned multiple patterning (SAMP) process is utilized for patterning structures, spacers formed adjacent mandrels, on a substrate. In one embodiment, a novel approach of etching titanium oxide (TiO) spacers is provided. Highly anisotropic etching of the spacer along with a selective top deposition is provided. In one embodiment, an inductively coupled plasma (ICP) etch tool is utilized. The etching process may be achieved as a one-step etching process. More particularly, a protective layer may be selectively formed on the top of the spacer to protect the mandrel as well as minimize the difference of the etching rates of the spacer top and the spacer bottom. In one embodiment, the techniques may be utilized to etch TiOspacers formed along amorphous silicon mandrels using an ICP etch tool utilizing a one-step etch process.

Method for highly anisotropic etching of titanium oxide spacer using selective top-deposition

A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCland hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.

Forming contact holes with controlled local critical dimension uniformity

A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

Extreme ultraviolet lithography patterning method

Methods are provided herein for improving oxygen content control in a Metal-Insulator-Metal (MIM) stack of an RERAM cell, while also maintaining throughput. More specifically, a single chamber solution is provided herein for etching and encapsulating the MIM stack of an RERAM cell to control the oxygen content in the memory cell dielectric of the RERAM cell. According to one embodiment, a non-oxygen-containing dielectric encapsulation layer is deposited onto the MIM stack in-situ while the substrate remains within the processing chamber used to etch the MIM stack. By etching the MIM stack and depositing the encapsulation layer within the same processing chamber, the techniques described herein minimize the exposure of the memory cell dielectric to oxygen, while maintaining throughput.

In-situ encapsulation of metal-insulator-metal (MIM) stacks for resistive random access memory (RERAM) cells

A method of forming a semiconductor device includes depositing a first layer over a substrate and patterning the first layer using an extreme ultraviolet (EUV) lithography process to form a patterned layer and expose portions of the substrate. The method includes, in a plasma processing chamber, generating a first plasma from a gas mixture including SiCl4 and one or more of argon, helium, nitrogen, and hydrogen. The method includes exposing the substrate to the first plasma to deposit a second layer including silicon over the patterned layer.

Methods of patterning small features

A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.

Method for patterning a dielectric layer

Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

ALD (atomic layer deposition) liner for via profile control and related applications

Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.

Split ash processes for via formation to suppress damage to low-K layers

Growing community of inventors

Mechanicville, NY, United States of America

Angelique Denise Raley