Xilinx, Inc.

Andrew W Lai

Tuyet Ngoc Simmons

Robert W Wells

Shekhar Bapat

Robert D Patrie

Randy J Simmons

Andy T Nguyen

Sridhar Krishnamurthy

Shahin Toutounchi

Jay T Young

Steven E McNeil

Shankar Lakkapragada

Jeffrey V Lindholm

Vincent L Tong

Michael Leonard Simmons

Teymour M Mansour

William R Troxel

Brian Sadler

Steven M Trimberger

In one embodiment a circuit for testing delays is provided. A test signal generator circuit toggles a plurality of output signals 1 through N in sequential order, separating the toggles by a delay period. Each output signal is coupled to an input of a respective one of a plurality of delay circuits. A phase detector circuit is coupled to the delay circuits and is configured to determine the order in which signals output from delay circuits X&#x2212;1, X, and X+1 are toggled for each delay circuit X. In response to the output signals being toggled in the order X&#x2212;1 followed by X followed by X+1, the phase comparator circuit is configured to output a first signal indicating correct operation. Otherwise, the phase comparator circuit is configured to output a second signal indicating incorrect operation.

Method and circuit for testing accuracy of delay circuitry

A method of testing an integrated circuit (IC) having a plurality of dies can include receiving, within a master die of the plurality of dies of the IC, a configuration data set specifying a circuit design, wherein the circuit design is instantiated within the master die. The method can include broadcasting the configuration data set to at least one slave die, wherein the circuit design is instantiated within each slave die and receiving, within the master die, a test vector set. The method also can include broadcasting the test vector set to the at least one slave die and responsive to each die executing the test vector set, storing test output data generated by each die.

Parallel testing of an integrated circuit that includes multiple dies

A test setup is provided to test differential signals outputs from the I/O block (IOB) pairs in an integrated circuit (IC). The test setup allows elimination of the external 100 Ohm resistors provided across the differential outputs on a device under test (DUT) test board containing the IC by taking advantage of a 100 Ohm resistor built into the IC between a portion of the IOB pairs. An IOB pair being tested may have its differential output terminal pair shorted to the differential output terminal pair of the IOBs having the internal 100 Ohm resistor.

Testing differential signal standards using device under test's built in resistors

In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a core module for providing one or more output signals. The device comprises an output logic module for receiving the one or more output signals and an input logic module, wherein the one or more output signals are received by the input logic module via one or more feedback paths, where the one or more output signals are forwarded back to the core module.

Method and apparatus for providing a feedback path for an output signal

Functional testing of an integrated circuit (IC) is a part from a more comprehensive and thorough testing. An IC including an embedded select circuit module coupled to receive numerous input signals. The IC may also include control circuit coupled to receive input control signals, where at least one input control signal of the input control signals is a mode signal. Asserting the mode signal may operate the select circuit module in a test mode.

Testing of an embedded multiplexer having a plurality of inputs

Method and apparatus for testing input/output circuits of an integrated circuit are described. An integrated circuit includes input/output circuits having input/output pads. The input/output pads are capable of being coupled together to a tester channel. The input/output circuits each are configurable via configuration circuitry to be in either a first mode or a second mode responsive to a select circuit of the configuration circuitry coupled to receive a first input for the first mode and a second input for the second mode. The select circuit is controlled responsive to a control select signal common to all or a portion of the select circuits of each of the input/output circuits.

Testing of input/output devices of an integrated circuit

Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of 'nanotechnology' and molecular-scale technology, or 'molectronics.' Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.

Application-specific methods for testing molectronic or nanoscale devices

Structures and methods for testing a re-programmable logic block embedded in a one-time programmable fabric in a PLD. The re-programmable logic block is tested without using the one-time programmable resources needed for implementing user circuits, by including a multiple input signature register (MISR) circuit coupled to receive output data from the re-programmable logic portion of the PLD. In some embodiments, a tester operating at a first and lower clock frequency can be used to test a re-programmable logic block operating at a second and higher clock frequency. In some of these embodiments, the one-time programmable fabric is tested at the first clock frequency.

Structures and methods for testing programmable logic devices having mixed-fabric architectures

Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.

Application-specific methods useful for testing look up tables in programmable logic devices

Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.

Methods of resource optimization in programmable logic devices to reduce test time

A method for accurate testing of the output voltage of an integrated circuit comprises enabling a differential voltage comparator on the integrated circuit to be tested. One input to the differential comparator is set to a reference voltage, and the other input is coupled to a node to be tested. A current load is injected at the node, and the output of the voltage comparator can be used to determine if the integrated circuit performs within the specifications set by a manufacturer.

Method for accurate output voltage testing

A new method to test short faults in a programmable logic device is described. The line segments under test are connected together to form a conducting chain. All the line segments neighboring to the conducting chain are tied to a known state. A test vector is applied to the programmable logic device. The state of the line under test is measured. If it is the same as the known state, the programmable logic device is likely to have faults.

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Fremont, CA, United States of America

Andrew W Lai