E Ink Corporation

Rf Micro Devices, Inc.

Qorvo Us, Inc.

Power Integrations, Inc.

Ss Sc Ip, LLC

Semisouth Laboratories, Inc.

Andrew P Ritenour

Gregg Michael Duthaler

Peter T Kazlas

Karl Raymond Amundson

David Charles Sheridan

Yu Chen

Kevin L Denis

Paul Stephen Drzaic

Nathan R Kane

Kevin Wesley Kobayashi

Guy Danner

Haldane S Henry

Casey Kirkpatrick

Kiran V Chatty

Jeffrey Casady

Janna Casady

Paul Partyka

Disclosed is a device that includes a crystalline substrate and a patterned aluminum-based material layer disposed onto the crystalline substrate. The patterned aluminum-based material layer has a titanium-alloyed surface. A titanium-based material layer is disposed over select portions of the titanium-alloyed surface. In an exemplary embodiment, the patterned aluminum-based material layer forms a pair of interdigitated transducers to provide a surface wave acoustic (SAW) device. The SAW device of the present disclosure is usable to realize SAW-based filters for wireless communication equipment.

Device having a titanium-alloyed surface

A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.

Semiconductor device with electrical overstress (EOS) protection

A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias.

Semiconductor device having improved heat dissipation

A backplane for an electro-optic display comprising pixels with reduced capacitance. The pixel architecture results in a backplane with some voltage spiking, but well-suited for use with electro-optic media having at least a small threshold for switching, for example, electrophoretic media comprising particles.

Backplane for electro-optic display

A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.

High voltage field effect transitor finger terminations

A Schottky gated transistor having reduced gate leakage current is disclosed. The Schottky gated transistor includes a substrate and a plurality of epitaxial layers disposed on the substrate. Further included is a gate contact having an interfacial layer disposed on a surface of the plurality of epitaxial layers and having a thickness that is between about 5 Angstroms (&#x212b;) and 40 &#x212b;. The interfacial layer can be made up of non-native materials in contrast to a native insulator such as silicon dioxide (SiO) that is used as an insulating gate layer with silicon-based power transistors. The Schottky gated transistor further includes at least one metal layer disposed over the interfacial layer. A source contact and a drain contact are disposed on the surface of the plurality of epitaxial layers, wherein the source contact and the drain contact are spaced apart from the gate contact and each other.

Schottky gated transistor with interfacial layer

An electro-optic display comprises a substrate (), non-linear devices () disposed substantially in one plane on the substrate (), pixel electrodes () connected to the non-linear devices (), an electro-optic medium () and a common electrode () on the opposed side of the electro-optic medium () from the pixel electrodes (). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices ().

Methods for forming patterned semiconductors

A gallium nitride (GaN) device with leakage current-based over-voltage protection is disclosed. The GaN device includes a drain and a source disposed on a semiconductor substrate. The GaN device also includes a first channel region within the semiconductor substrate and between the drain and the source. The GaN device further includes a second channel region within the semiconductor substrate and between the drain and the source. The second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region. As a result, a drain voltage will be safely clamped below a destructive breakdown voltage once a substantial drain current begins to flow through the second channel region.

Gallium nitride (GaN) device with leakage current-based over-voltage protection

The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside.

Power device packaging having backmetals couple the plurality of bond pads to the die backside

High voltage field effect transistor finger terminations

A lateral semiconductor device having a vertical region for providing a protective avalanche breakdown (PAB) is disclosed. The lateral semiconductor device has a lateral structure that includes a conductive substrate, semi-insulating layer(s) disposed on the conductive substrate, device layer(s) disposed on the semi-insulating layer(s), along with a source electrode and a drain electrode disposed on the device layer(s). The vertical region is separated from the source electrode by a lateral region wherein the vertical region has a relatively lower breakdown voltage level than a relatively higher breakdown voltage level of the lateral region for providing the PAB within the vertical region to prevent a potentially damaging breakdown of the lateral region. The vertical region is structured to be more rugged than the lateral region and thus will not be damaged by a PAB event.

Lateral semiconductor device with vertical breakdown region

Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.

Methods for fabricating high voltage field effect transistor finger terminations

A method for wafer high voltage testing of semiconductor devices is disclosed. The method involves adding a patterning layer onto a passivation layer of the semiconductor devices and then etching vias through the passivation layer to expose conductive test points. Testing of the semiconductor devices begins with engaging the conductive test points with high voltage test probes of a testing apparatus and then applying a high voltage test sequence to the conductive test points via the high voltage test probes. The testing of the semiconductor devices concludes by disengaging the high voltage test probes from a last one of the semiconductor devices and then removing the patterning layer from the passivation layer of the semiconductor devices.

Growing community of inventors

Colfax, NC, United States of America

Andrew P Ritenour