International Business Machines Corporation

Infineon Technologies Ag

Other

Andrew P Cowley

Lawrence Alfred Clevenger

Chih-Chao Yang

Timothy Joseph Dalton

Kaushik Chanda

Baozhen Li

Jason Paul Gill

Erdem Kaltalioglu

Hazara Singh Rathore

Paul Stephen McLaughlin

Meeyoung H Yoon

Timothy Dooling Sullivan

Andrew Herbert Simon

Ronald G Filippi

Tom C Lee

Kaushik Arun Kumar

Douglas C La Tulipe, Jr

Mark Hoinkis

Du Binh Nguyen

Birendra N Agarwala

Steffen K Kaldor

Clement Hsingjen Wann

Terry Allen Spooner

Yun-Yu Wang

Vincent James McGahay

Jochen Schacht

Peter A Emmi

Stephen Mark Rossnagel

Robert Daniel Edwards

Conrad A Barile

Chih-Chao c/o Ibm United Kingdom Limited Yang

The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.

Method for prediction of premature dielectric breakdown in a semiconductor

A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

Via bottom contact and method of manufacturing same

A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

Structure for modeling stress-induced degradation of conductive interconnects

A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (&#x3bc;m).

Structure for monitoring stress-induced degradation of conductive interconnects

A structure. The structure includes: a core electrical conductor having a top surface, an opposite bottom surface and sides between the top and bottom surfaces; an electrically conductive liner in direct physical contact with and covering the bottom surface and the sides of the core electrical conductor, embedded portions of the electrically conductive liner in direct physical contact with and extending over the core electrical conductor in regions of the core electrical conductor adjacent to both the top surface and the sides of the core electrical conductor; and an electrically conductive cap in direct physical contact with the top surface of the core electrical conductor that is exposed between the embedded portions of the electrically conductive liner.

Interconnect structure

VIA bottom contact and method of manufacturing same

A method of forming a damascene wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor.

Method of fabrication of interconnect structures

A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

Interconnect structure and method of fabrication of same

An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Back end interconnect with a shaped interface

Structure and method for monitoring stress-induced degradation of conductive interconnects

A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 &#x3bc;Ohm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing Nand a flow rate such that (Nflow)/(N+carrier flow)&#x3e;0.5.

Crystallographic modification of hard mask properties

An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.

Method of forming an on-chip decoupling capacitor with bottom hardmask

On-chip decoupling capacitor with bottom hardmask

Growing community of inventors

Wappingers Falls, NY, United States of America

Andrew P Cowley