Irvine Sensors Corporation

Other

Andrew N Camien

James S Yamaguchi

Volkan H Ozguz

Angel Antonio Pepe

W Eric Boyd

Douglas Marice Albert

A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Stackable semiconductor chip layer comprising prefabricated trench interconnect vias

A method is disclosed for providing electrical connections to electronic elements within a multilayer module. The method includes providing first and second active layers having first and second edges, respectively. Each active layer includes a flexible, polymer substrate and at least one electronic element formed within the substrate. Electrically-conductive traces provide electrical connections from the first and second edges to the electronic elements. An adhesive is applied to at least one of a top surface of the first active layer and a bottom surface of the second active layer and the top surface of the first active layer is adhered to the bottom surface of the second active layer. The first edge and the second edge are aligned with each other thereby forming a side of the multilayer module. Electrically-conductive lines are applied along the side of the multilayer module to provide electrical connections to the traces.

Process of manufacturing multilayer modules

A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.

Multilayer modules with flexible substrates

Each multilayer module of a plurality of multilayer modules has a plurality of layers wherein each layer has a substrate therein. The plurality of multilayer modules includes a first multilayer module including a first layer and a second multilayer module including a second layer each having a top side and bottom side. The first layer and second layer each includes a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The plurality of multilayer modules further includes a heat-separating layer disposed between the top side of the first layer and the bottom side of the second layer. The first multilayer module is adhered to the second multilayer module and the first multilayer module can be detached from the second multilayer module by applying heat to the heat-separating layer.

Stacking of multilayer modules

A stack of multilayer modules has a segmentation layer disposed between neighboring multilayer modules. The segmentation layer facilitates the separation of neighboring multilayer modules. The stack of multilayer modules includes a first multilayer module and a second multilayer module. Each multilayer module includes a plurality of active layers each comprising a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The second multilayer module is disposed to be neighboring the first multilayer module with at least one segmentation layer between the first and second multilayer modules. The segmentation layer includes a metal layer and at least one thermoplastic adhesive layer. When heat is applied, the metal layer conducts heat to the thermoplastic adhesive layer.

Stack of multilayer modules with heat-focusing metal layer

A method and structure are disclosed which involve the re-wafering of previously processed and tested IC chips. The chips are encapsulated in supporting non-conductive material in a neo-wafer, so that they may be further processed preparatory to dicing layer units from the neo-wafer, which layer units are ready for stacking in a three-dimensional electronic package. Although the layer areas are the same, different stacked layers may contain different sized IC chips, and a single layer may encapsulate a plurality of chips. Precision of location of the separate IC chips in the neo-wafer is insured by use of photo-patterning means to locate openings in the neo-wafer into which extend conductive bumps on the chips. The neo-wafer is preferably formed with separate cavities in which the chips are located before they are covered with the encapsulating material.

Stackable layers containing encapsulated chips

Neo-chips suitable for stacking in 3D multi-layer electronic modules are formed by embedding (encapsulating ) IC chips in epoxy material which provides sufficient layer rigidity after curing. The encapsulated chips are formed by placing separate IC chips, usually 'known good' die, in a neo-wafer, which is subjected to certain process steps, and then diced to form neo-chips. The following benefits are obtained: (1) The starting IC chips (die) intended for stacking may have different sizes, and serve different electronic purposes. After they are encapsulated in same-size neo-chips, they can be efficiently stacked using well-developed processing steps; (2) The individual chips for stacking can be purchased as 'known good' die. This means than an essentially unlimited choice of die is available to the stacking entity, and that the die are pretested when they are ready for stacking; (3) A given layer can contain a plurality of individual die; and (4) The die encapsulating material is dielectric, so that no special steps are required to prepare the access plane of the stack for metalization. Heretofore, this preparation of the access plane has required either the etch-back plus passivation process, or the passivation plus trench-formation process.

Stack of equal layer neo-chips containing encapsulated IC chips of

Neo-chips suitable for stacking in 3D multi-layer electronic modules are formed by embedding (encapsulating) IC chips in epoxy material which provides sufficient layer rigidity after curing. The encapsulated chips are formed by placing separate IC chips, usually 'known good' die, in a neo-wafer, which is subjected to certain process steps, and then diced to form neo-chips. The following benefits are obtained: (1) The starting IC chips (die) intended for stacking may have different sizes, and serve different electronic purposes. After they are encapsulated in same-size neo-chips, they can be efficiently stacked using well-developed processing steps; (2) The individual chips for stacking can be purchased as 'known good' die. This means than an essentially unlimited choice of die is available to the stacking entity, and that the die are pretested when they are ready for stacking; (3) A given layer can contain a plurality of individual die; and (4) The die encapsulating material is dielectric, so that no special steps are required to prepare the access plane of the stack for metalization. Heretofore, this preparation of the access plane has required either the etch-back plus passivation process, or the passivation plus trench-formation process.

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Costa Mesa, CA, United States of America

Andrew N Camien