Micron Technology Incorporated

Andrew M Bayless

Brandon P Wirz

James M Derderian

Xiao Li

Owen R Fay

Cassie L Bayless

Sanh D Tang

John K Zahurak

Ming Zhang

Joseph M Brand

Wayne H Huang

Ruei Ying Sheng

Kyle K Kirby

Wei Zhou

Xiaopeng Qu

Hyunsuk Chun

Bradley R Bitz

Sharon N Farrens

Neal Bowen

Bang-Ning Hsu

A semiconductor device assembly can include an assembly semiconductor die having a top surface with a first and a second assembly communication element thereat. The semiconductor device assembly can further include a semiconductor die stack coupled to the top surface. The die stack can include a first and a second semiconductor die, each having a top surface perpendicular to the top surface of the assembly semiconductor die. Further, the first semiconductor die can have a first die communication element aligned with and configured to directly communicate with the first assembly communication element, and the second semiconductor die can have a second die communication element aligned with and configured to directly communicate with the second assembly communication element.

Perpendicular semiconductor device assemblies and associated methods

A microelectronic device may have side surfaces each including a first portion and a second portion. The first portion may have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion may have a less uneven surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming the microelectronic device may include creating dislocations in the wafer in a street between the one or more microelectronic devices by implanting ions and cleaving the wafer responsive to failure of stress concentrations near the dislocations through application of heat, tensile forces or a combination thereof. Related packages and methods are also disclosed.

Microelectronic devices and related methods of fabricating microelectronic devices

Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

Semiconductor die edge protection for semiconductor device assemblies and associated systems and methods

Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.

Semiconductor devices with recessed pads for die stack interconnections

This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

Substrates with heat transfer structures for bonding a stack of microelectronic devices, and related assemblies and electronic systems

Methods for releasing thinned semiconductor dies from a mount tape and associated apparatuses are disclosed. In one embodiment, a sacrificial layer may be disposed at a back side of thinned substrate including semiconductor dies. The sacrificial layer includes materials soluble in contact with a fluid (and/or vapor). A sheet of perforated mount tape may be attached to the sacrificial layer and an ejection component may be provided under a target semiconductor die to be released. The ejection component is configured to create a locally confined puddle of the fluid under the target semiconductor die such that the sacrificial layer is removed to release the target semiconductor die from the mount tape. Further, a support component may be provided to pick up the target semiconductor die after the target semiconductor die is released from the mount tape.

Thin die release for semiconductor device assembly

Singulated integrated circuit (IC) dice are provided. The singulated IC dice are positioned on dicing tape to provide open space between sides of adjacent singulated IC dice. An underfill layer and a protective cover film is disposed above the singulated IC dice and the open space between the sides of the adjacent singulated IC dice. The underfill layer and the protective cover film include one or more photodefinable materials. An exposure operation is performed to produce a pattern on the underfill layer and the protective cover film. Based on the pattern, the underfill layer and the protective cover film is removed at areas above the open space between the sides of the adjacent singulated IC dice to create portions of the underfill layer and portions of the protective cover film that are disposed above the singulated IC dice.

Disposing protective cover film and underfill layer over singulated integrated circuit dice for protection during integrated circuit processing

Method of fabricating microelectronic devices and related microelectronic devices, tools, and apparatus

Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

Method for semiconductor die edge protection and semiconductor die separation

A method for separating semiconductor die stacks of a chip-on-wafer assembly is disclosed herein. In one example, divider walls are arranged in a pattern on a first surface of a device wafer such that regions between the divider walls define mounting sites. Die stacks are mounted to the device wafer, wherein individual die stacks are located at a corresponding mounting site between the divider walls. The device wafer is cut through from a second surface that is opposite the first surface of the device wafer, and the divider walls are removed from between the die stacks to form a vacant lane between adjacent die stacks.

Separation method and assembly for chip-on-wafer processing

Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.

Recessed semiconductor devices, and associated systems and methods

This patent application relates to methods and apparatus for temperature modification and reduction of contamination in bonding stacked microelectronic devices with heat applied from a bond head of a thermocompression bonding tool. The stack is substantially enclosed within a skirt carried by the bond head to reduce heat loss and contaminants from the stack, and heat may be added from the skirt.

Growing community of inventors

Boise, ID, United States of America

Andrew M Bayless