International Business Machines Corporation

Globalfoundries Inc.

Renesas Electronics Corporation

Toshiba America Electronic Components, Inc.

Andres Bryant

Edward J Nowak

Brent A Anderson

William F Clark, Jr

John J Ellis-Monaghan

Minh H Tong

Jed Hickory Rankin

James William Adkisson

Mark David Jaffe

Anthony K Stamper

Jeffrey Bowman Johnson

Tenko Yamashita

Robert J Gauthier, Jr

Jeffrey P Gambino

Effendi Leobandung

Veeraraghavan S Basker

Jeffrey W Sleight

Kerry Bernstein

Alain F Loiseau

Randy William Mann

Robert Russell Robison

Wilfried Haensch

Wilbur David Pricer

Huiming Bu

K Paul Muller

David Michael Fried

Jerome Brett Lasky

Peter Edwin Cottrell

Chun-chen Yeh

Arvind Kumar

Omer H Dokumaci

Fariborz Assaderaghi

Edward P Maciejewski

Mickey H Yu

Theodorus E Standaert

Steven H Voldman

Shreesh Narasimha

Meikei Ieong

Richard Quimby Williams

Hussein Ibrahim Hanafi

Jeffrey Scott Brown

Nivo Rovedo

William A Klaasen

Hasan Munir Nayfeh

Josephine B Chang

Sivananda K Kanakasabapathy

Kern Rim

Dominic Joseph Schepis

Chung-Hsun Lin

Herbert Lei Ho

John Joseph Pekarik

Renee Tong Mo

Oki Gunawan

Qiqing Christine Ouyang

Wayne John Howell

Christopher Stephen Putnam

Richard A Phelps

Myung-Hee Na

Atul Champaklal Ajmera

Michael Abramovich Gribelyuk

Shih-Hsien Lo

Percy V Gilbert

Jiale Liang

Guy M Cohen

Dechao Guo

Michael A Guillorn

Kirk David Peterson

Edmund Juris Sprogis

Brian Joseph Greene

Sarunya Bangsaruntip

Anthony I Chou

Mark B Ketchen

Gen Tsutsui

John S Foster

Jia Chen

Jane Elizabeth Frommer

Ronald Jay Bolam

Scott R Stiffler

Lyndon Ronald Logan

Shih-Fen Huang

William D Clark

Patrick C Arnett

Ryoji Hasumi

Alain Loiseau

Jon A Iwata

Alain Lolseau

A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

FINFET having a gate structure in a trench feature in a bent fin

A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

Structure and method to form a FinFET device

An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

FDSOI voltage reference

Method of fabricating a FINFET having a gate structure disposed at least partially at a bend region of the semiconductor fin

A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch. A second double density pattern of second sidewall spacers is produced on a layer disposed above the first double density pattern from second mandrels formed by a second mask with a the minimum pitch that is shifted relative to the first mask. A single sidewall spacer is removed from either the first or second double density pattern of first and second sidewall spacers. Sidewall image transfer processes allow the formation of quadruple density fins from which but a single fin is removed.

Method for quadruple frequency FinFETs with single-fin removal

An asymmetrical finFET device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The fin extends along a length of the semiconductor substrate to define a fin length. A plurality of gate structures wrap around the sidewalls and upper fin surface of the fin. The plurality of gate structures includes at least one desired gate structure surrounded by at least one sacrificial gate structure. A first source/drain region is formed adjacent a first sidewall of the at least one desired gate structure, and a second source/drain region is formed adjacent a second sidewall of the at least one desired gate structure opposite the first sidewall. The dimensions of the first and second source/drain regions are asymmetrical with respect to one another.

Asymmetric multi-gate FinFET

In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first FET (e.g., a NFET) and a second gate sidewall spacer for a second FET (e.g., a PFET) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first FET are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second FET are formed immediately following second gate sidewall spacer formation. Since the gate sidewall spacers of the two FETs are symmetric, the source/drain junctions of the two FETs will also be symmetric. Additionally, due to an etch stop layer formed on the raised source/drain regions of the first FET, but not the second FET, different metal silicides on the raised source/drain regions of the different FETs.

Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides

Asymmetric multi-gate finFET

A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening

A structure includes at least one shallow trench isolation structure formed in a substrate to isolate adjacent different type devices. The structure further includes a barrier trench structure formed in the substrate to isolate diffusions of adjacent same type devices. The structure further includes a material spanning the barrier trench structure to connect the diffusions of the adjacent same type device, on a same level as the adjacent same type devices.

Barrier trench structure and methods of manufacture

A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.

Method, structure and design structure for customizing history effects of SOI circuits

Merged fin structures for finFET devices and methods of manufacture are disclosed. The method of forming the structure includes forming a plurality of fin structures on an insulator layer. The method further includes forming a faceted structure on adjacent fin structures of the plurality of fin structures. The method further includes spanning a gap between the faceted structures on the adjacent fin structures with a semiconductor material.

Merged fin structures for finFET devices

Growing community of inventors

Burlington, VT, United States of America

Andres Bryant