Infineon Technologies Ag

Kabushiki Kaisha Toshiba

Other

Infineon Ag

Andreas Hilliger

Nicolas Nagel

Uwe Wellhausen

Rainer Bruchhaus

Gerhard Beitel

Stefan Gernhardt

Jingyu Lian

Koji Yamakawa

Jenny Lian

Karl Hornik

Bum-ki Moon

Keitaro Imai

Hiroyuki Kanaya

Haoren Zhuang

Ulrich Egger

Moto Yabuki

Bum-Ki Moon

Takamichi Tsuchiya

Bum Ki Moon

Tohru Ozaki

Thomas Roehr

Kazuhiro Tomioka

Hiroshi Itokawa

Yoshinori Kumura

Michael Jacob

Joerg W Wohlfahrt

Toru Ozaki

Ralf Staub

Eike Lüken

Susumo Shuto

An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.

Self-aligned V0-contact for cell size reduction

A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material in the contact hole, and filling the contact hole with a conductive material. A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids in an existing barrier layer caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.

Formation of a contact in a device, and the device including the contact

The invention relates to a method for producing an integrated circuit comprising the following steps: preparing a semi-conductor substrate () with a contacting circuit area (SS); providing an insulating layer (IS) on the surface of the semi-conductor substrate (): providing a contact hole (KL) in the insulating layer (IS) for making contacting the circuit area (SS); providing an insulating spacer area (') in at least the area above the contact hole (KL); providing at least three trenches (BG; BG; BG), the first (BG) of which is arranged next to the contact hole (KL), a second (BG) is disposed across the contact hole (KL) and a third (BG) is next to the contact hole (KL). The spacer area (&#x2032;) is placed between the first and the second trench (BG; BG) and the second and the third trench (BG; BG); filling the trenches (BG; BG; BG) with a conductive material; and chemical-mechanical polishing of conductive material for producing three separated trenches (BL; BL; BL).

Method for producing an integrated circuit

A ferroelectric capacitor device comprises a substrate, a contact plug passing through the substrate, a first electrode formed on the substrate, the first electrode being electrically connected to said plug, a ferroelectric layer formed on the first electrode, a second electrode formed on the ferroelectric layer, one or more first encapsulation layers on the second electrode, the encapsulation layers extending over the device, and one or more hydrogen storage material layers on the encapsulation layers. One or more second encapsulation layers may be formed on the one or more hydrogen storage material layers.

Device for inhibiting hydrogen damage in ferroelectric capacitor devices

An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.

Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

Semiconductor device

The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.

Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole reactive ion etch processing

An improved barrier stack for inhibiting diffusion of atoms or molecules, such as Ois disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with Ousing, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer. The second barrier layer comprises a conductive oxide.

Barrier stack with improved barrier properties

A ferroelectric capacitor device, such as an FeRAM device is formed of a substrate having one or more contact plugs extending therethrough, and a first interlayer dielectric layer formed on the substrate. A spacer layer is formed on the first interlayer dielectric layer, a first oxygen barrier layer is formed on the spacer layer and a buffer layer is formed on the first oxygen barrier layer. A layer of liner material is formed on the buffer layer between the buffer layer and the contact plugs and a dielectric layer is sandwiched between a first electrode and a second electrode. A second oxygen barrier layer is applied to the device. The spacer layer should prevent any oxidation from reaching the interface between the liner material and the contact plugs as this interface is located beneath the first oxygen barrier layer. As a result, the electrical contact is not damaged.

Ferroelectric capacitor devices and FeRAM devices

The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.

Side-wall barrier structure and method of fabrication

Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate, an insulation region which covers the capacitor and has a first hole and a second hole, the first hole being provided apart from the capacitor and extending in a vertical direction with respect to a main surface of the semiconductor substrate, the second hole reaching an electrode of the capacitor, extending in the vertical direction with respect to the main surface of the semiconductor substrate and being shallower than the first hole, a tungsten plug provided in the first hole, a first oxygen barrier film provided between the tungsten plug and a side wall of the first hole, and a conductive plug provided in the second hole and connected to the electrode of the capacitor.

Semiconductor device and method of manufacturing the same

A memory cell having capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion region of a transistor by a bottom electrode plug. A dielectric layer covers the capacitor. Above the dielectric layer is a first barrier layer. A via is created in the dielectric layer in which a plug is formed to couple to the second diffusion region. The via comprises substantially vertical sidewalls. A second barrier layer lines the sidewalls of the via. A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.

Ferroelectric memory integrated circuit with improved reliability

First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor substrate which lies between the first and second semiconductor regions. An interlayer insulating film is formed on the semiconductor substrate to cover the first and second semiconductor regions and the gate electrode. First and second lower electrodes are formed on the interlayer insulating film. A first contact plug is formed in the interlayer insulating film in contact with the first lower electrode. A second contact plug is formed in the interlayer insulating film in contact with the second lower electrode. A first ferroelectric film is formed on the first lower electrode. A first upper electrode is formed on the first ferroelectric film. A second ferroelectric film is formed on the second lower electrode. A second upper electrode is formed on the second ferroelectric film.

Semiconductor device having ferroelectric film and manufacturing method thereof

A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.

Multi-layer barrier allowing recovery anneal for ferroelectric capacitors

An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.

Growing community of inventors

Kanagawa-ken, Japan

Andreas Hilliger