International Business Machines Corporation

Mentor Graphics Corporation

Globalfoundries Inc.

Freescale Semiconductor,inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Infineon Technologies North America Corp.

Anda C Mocuta

Dureseti Chidambarrao

Paul S Chang

Dan Mihai Mocuta

Diane Catherine Boyd

Ricky S Amos

Effendi Leobandung

Jason D Hibbeler

James A Culp

Praveen Elakkumanan

Anthony K Stamper

Huilong Zhu

Jeffrey W Sleight

Vijay Narayanan

Terence B Hook

Cyril Cabral, Jr

Kern Rim

Ying Li

Xiaojun Yu

An L Steegen

Jakub Tadeusz Kedzierski

Victor Ku

Richard D Kaplan

Woo-Hyeong Lee

Carl John Radens

Stephen W Bedell

Meikei Ieong

Huajie Chen

Jae-Eun Park

Paul Andrew Ronsheim

Heemyong Park

Jie Deng

Sim Y Loo

Terrence B Hook

Maheswaren Surendra

Ghavam G Shahidi

Haining S Yang

Kevin K Chan

Haizhou Yin

Toshiaki Kirihata

Xiangdong Chen

Jack Oon Chu

Tze-Chiang Chen

Qiqing Christine Ouyang

John Albrecht Ott

Dae-Gyu Park

Voon-Yew Thean

Werner A Rausch

Kenneth Jay Stein

Maheswaran Surendra

Jin-Ping Han

Anthony Gene Domenicucci

Yong Meng Lee

Da Zhang

Ricardo Alves Donaton

Kam-Leung Lee

Young Way Teh

Laegu Kang

Mukesh Vijay Khare

David M Onsongo

Melanie J Sherony

Weipeng Li

Byoung Hun Lee

Thomas T Hwang

Franck Arnaud

Silke H Christianson

A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors

Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Methods and system for analysis and management of parametric yield

An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.

Intra die variation monitor using through-silicon via

The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Balancing NFET and PFET performance using straining layers

A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator ('SOI') layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ('PFET') and the SOI device includes an n-type field effect transistor (&#x201c;NFET&#x201d;) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Protection against charging damage in hybrid orientation transistors

In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region. The second diode may be connected in a reverse-biased orientation to a source region or a drain region of an NFET.

Method of providing protection against charging damage in hybrid orientation transistors

The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be SiGeZ, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

MOSFET with super-steep retrograded island

A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

High performance strained silicon FinFETs device and method for forming same

The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

CMOS silicide metal gate integration

Growing community of inventors

Lagrangeville, NY, United States of America

Anda C Mocuta