Unisem (mauritius) Holdings Limited

Advanced Interconnect Technologies Limited

Unisem (mauritus) Holdings Limited

Anang Subagio

Romarico Santos San Antonio

Shafidul Islam

Michael H McKerreghan

Mary Jean Bajacan Ramos

Mary Jean Ramos

Allan C Toriaga

Timothy Leung

Daniel K Lau

Lenny Christina Gultom

Lynn Simporios Guirit

Gan Kian Yeow

Kyaw Ko Lwin

Glenn Macaraeg

Edmunda G-o Litilit

A redistributed lead frame for use in a molded plastic semiconductor package is formed from an electrically conductive substrate by a sequential metal removal process. The process includes patterning a first side of the substrate to form an array of lands separated by channels; disposing a first molding compound within those channels; patterning a second side of the substrate to form an array of chip attach sites and routing circuits electrically interconnecting the array of lands and the array of chip attach sites; directly electrically interconnecting input/output pads on a semiconductor device to the chip attach sites; and encapsulating the semiconductor device, the array of chip attach sites and the routing circuits with a second molding compound. This process is particularly suited for the manufacture of chip scale packages and very thin packages.

Lead frame routed chip pads for semiconductor packages

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.

Partially patterned lead frames and methods of making and using the same in semiconductor packaging

A method for manufacturing a semiconductor device package to provide RF shielding. The device is mounted on a laminated substrate having conducting pads on its top surface. A molding compound covers the substrate top surface and encapsulates the devices. The substrate is disposed on a tape; the molding compound and the substrate are cut through, forming package units separated by the saw cut width and exposing a portion of a conducting pad. In an embodiment, the tape is stretched to widen the gap between package units. A conductive shield is applied to cover each package unit and to make electrical contact with the exposed conducting pad portion, thereby connecting to a ground trace beneath the device and providing RF shielding for the device. A single-unit molding process may be used, in which the conducting pad is exposed during and after molding.

RF shielding for a singulated laminate semiconductor device package

A no-lead electronic package including a heat spreader and method of manufacturing the same. This method includes the steps of selecting a matrix or mapped no-lead lead frame with die receiving area and leads for interconnect; positioning an integrated circuit device within the central aperture and electrically interconnecting the integrated circuit device to the leads; positioning a heat spreader in non-contact proximity to the integrated circuit device such that the integrated circuit device is disposed between the leads and the heat spreader; and encapsulating the integrated device and at least a portion of the heat spreader and leads in a molding resin.

No lead package with heat spreader

A package to encase a semiconductor package is manufactured by the following steps. First, an electrically conductive frame is provided. This frame has a plurality of leadframes arranged in a matrix with each leadframe having a plurality of spaced leads extending outwardly from a central aperture. The electrically conductive frame further includes a plurality of connecting bars joining outer end portions of adjacent ones of the leadframes. Second, a groove is formed in the connecting bars to form a reduced thickness portion between the outer end portions of adjacent ones of the leadframes. Third, a semiconductor device is electrically coupled to inner portions of said leads. Fourth, the frame and the semiconductor devices are encapsulated in a molding compound. Finally, the molding compound and the frame are cut along the grooves to form singulated semiconductor packages having outer lead portions with a height greater than the height of the reduced thickness portion.

Leadless semiconductor package and method of manufacture

A redistributed lead frame for use in a molded plastic semiconductor package () is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound () within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites () and routing circuits () electrically interconnecting the array of lands and the array of chip attach sites (), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device () to chip attach site members () of the array of chip attach sites (), and (e) encapsulating the at least one semiconductor device (), the array of chip attach sites () and the routing circuits () with a second molding compound (). This process is particularly suited for the manufacture of chip scale packages and very thin packages.

A method to manufacture a package that encases at least one integrated circuit device and the package so manufactured. The method includes the steps of (1) providing a leadframe having a die pad, leads, at least one ring circumscribing the die pad and disposed between the die pad and the leads, a plurality of tie bars projecting outwardly from the at least one ring, and at least one connecting bar electrically interconnecting and mechanically supporting the die pad to the ring; (2) affixing the at least one integrated circuit device to a first side of the die pad and electrically interconnecting the at least one integrated circuit device to the leads and to the at least one ring; (3) encapsulating the at least one integrated circuit device, the first side of the die pad and a first side of the ring in a molding resin while retaining an opposing second side of the ring external to said molding resin; and (4) severing the at least one connecting bar to electrically isolate the die pad from the ring.

Method for making QFN package with power and ground rings

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, in contrast with the conventional fully etched stencil-like lead frames, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal. The use of the instant partially patterned lead frame in making ELP, ELPF and ELGA-type CSPs is also disclosed.

A redistributed lead frame for use in molded plastic semiconductor package () is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound () within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites () and routing circuits () electrically interconnecting the array of lands and the array of chip attached sites (), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device () to chip attach site members () of the array of chip attach sites (), and (e) encapsulating the at least one semiconductor device (), the array of chip attach sites () and the routing circuits () with a second molding compound (). This process is particularly suited for the manufacture of chip scale packages and very thin packages.

An array-type package encasing one or more semiconductor devices. The package includes a dielectric substrate having opposing first and second sides with a plurality of electrically conductive vias and a centrally disposed aperture extending from the first side to the second side. A heat slug has a mid portion extending through the aperture, a first portion adjacent the first side of the substrate with a cross sectional area larger than the cross sectional area of the aperture and an opposing second portion adjacent the second side of the substrate. One or more semiconductor devices are bonded to the first portion of the heat slug and electrically interconnected to the electrically conductive vias. A heat spreader having a first side and an opposing second side is spaced from the semiconductor devices and generally parallel with the heat slug, whereby the semiconductor devices are disposed between the heat spreader and the heat slug. A molding resin encapsulates the semiconductor devices and at least the first side of the substrate, the first portion of the heat slug and the first side of the heat spreader.

Method of making thermally enhanced substrate-base package

A method for the manufacture of a package to encapsulate at least one integrated circuit device includes the steps of: (1) providing a dielectric substrate having a first plurality of bond pads formed on a first side thereof and at least one aperture; (2) electrically interconnecting the integrated circuit device to the plurality of bond pads forming a substrate/integrated circuit device assembly; (3) gravitationally aligning the substrate/integrated circuit assembly such that the integrated circuit device is lower than said substrate; (4) introducing a volume of a low viscosity dielectric into the at least one aperture, wherein the volume is effective to coat a surface of the integrated circuit device and substantially fill the at least one aperture; and (5) encapsulating the integrated circuit device and the first side of said substrate with a dielectric polymer.

Method of making flip-chip package with underfill

A lead frame () for a semiconductor device (die) package () is described. Each of the leads () in the lead frame () includes an interposer () having one end () disposed proximate the outer face () of the package () and another end () disposed proximate the die (). Extending from opposite ends of the interposer () are a board connecting post () and a support post (). A bond site () is formed on a surface of the interposer () opposite the support post (). Each of the leads () is electrically connected to an associated input/output (I/O) pad () on the die () via wirebonding, tape bonding, or flip-chip attachment to the bond site (). Where wirebonding is used, a wire electrically connecting the I/O pad () to the bond site () may be wedge bonded to both the I/O pad () and the bond site (). The support post () provides support to the end () of the interposer () during the bonding and coating processes.(FIG.).

Semiconductor device package and method for manufacturing same

A semiconductor device package comprising a semiconductor device and an electrically conductive lead frame at least partially covered by a molding compound. The electrically conductive lead frame includes a plurality of leads disposed proximate a perimeter of the package and a die pad disposed in a central region formed by the plurality of leads. The die pad includes a first die pad surface disposed at the first package face, and a second die pad surface opposite the first die pad surface. The semiconductor device is attached to a central region of the second die pad surface, and a portion of the second die pad surface extending outward from the die is roughened to improve adhesion of the die pad to the molding compound. In other aspects, grooves are disposed in the first and/or second die pad surfaces to further promote adhesion of the die pad and to prevent moisture from permeating into the vicinity of the semiconductor chip. The die pad may further include tie bars extending therefrom, and at least one lip at may extend from a side surface of the die pad to anchor the die pad in the molding compound. The die pad may also include apertures disposed therein for allowing the egress of moisture from the package.

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Batam Island, Indonesia

Anang Subagio