Intel Corporation

Daedalus Prime LLC

Sony Group Corporation

Tahoe Research, Ltd.

Sony Corporation

Intel Corproation

Anand S Murthy

Tahir Ghani

Glenn A Glass

Jack T Kavalieros

Willy Rachmady

Gilbert W Dewey

Matthew V Metz

Chandra S Mohapatra

Karthik Jambunathan

Harold W Kennel

Cory C Bomberger

Robert S Chau

Sean T Ma

Daniel Bourne Aubertine

Cheng-Ying Huang

Biswajeet Guha

Seiyon Kim

Boyan Boyanov

Stephen M Cea

Kelin J Kuhn

Seung Hoon Sung

Ashish Agrawal

Nicholas G Minutillo

Benjamin Chu-Kung

Siddharth Chouksey

Ryan Keech

Brian S Doyle

Patrick R Morrow

Anupama Bowonder

Rafael Rios

Rishabh Mehandru

Abhijit Jayant Pethe

Roza Kotlyar

Mark T Bohr

Michael L Hattendorf

Mark Y Liu

Mark Armstrong

Suman Datta

Chia-Hong Jan

Cory E Weber

Nadia M Rahhal-Orabi

Mauro J Kobrinsky

Nick Lindert

Paul A Packan

Justin K Brask

Prashant Majhi

Been-Yih Jin

Sanaz Kabehie Gardner

Shaofeng Yu

Subhash M Joshi

Nazila Haratipour

Kaizad Rumy Mistry

Shahriar S Ahmed

Aaron D Lilak

Bernhard Sell

Christopher J Jezewski

Annalisa Cappellani

Jun Sung Kang

Ritesh Jhaveri

Ravi Pillarisetty

Marko Radosavljevic

Van H Le

Niloy Mukherjee

Kimin Jun

Szuya S Liao

Ehren Mannebach

Richard E Green

Brian E Roberds

Steven J Keating

Jack Hwang

Aaron A Budrevich

Stephen T Chambers

Han Wui Then

Mark L Doczy

Wilfred Gomes

Anh Phan

Dax M Crum

Gopinath Bhimarasetti

Justin R Weber

Arnab Sen Gupta

Pratik A Patel

Srijit Mukherjee

Thomas A Letson

Harry Gomez

Abhishek A Sharma

Sansaptak W Dasgupta

Walid M Hafez

Paul B Fischer

Nicole K Thomas

Huang-Lin Chao

Ebrahim Andideh

William Hsu

Joseph M Steigerwald

Patrick H Keys

Bruce E Beattie

Andy Chih-Hung Wei

Nancy M Zelick

Jenny Hu

Pushkar Ranade

Chung-Hsun Lin

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a relatively high germanium content are described. In an example, an integrated circuit structure includes a fin including a semiconductor material. A gate stack is over an upper fin portion of the fin. A first epitaxial source or drain structure is embedded in the fin at a first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at a second side of the gate stack. The first and second epitaxial source or drain structures include silicon and germanium and have a same or greater atomic concentration of germanium than the fin.

Source or drain structures with relatively high germanium content

IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

Integrated circuit devices with angled transistors formed based on angled wafers

Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Integrated circuit structures having ultra-high conductivity global routing

Multi-plate MIM capacitors include a staircase structure, with steps including a high-k capacitor dielectric and one or more electrode plates. Contacts pass through insulator fill material and land on the electrode plate of a respective step. A recess passes through the staircase structure. In some examples, the recess is filled with insulator material, and steps of the staircase structure have a bilayer structure (e.g., lower layer of capacitor dielectric and upper layer of capacitor electrode plate). In other examples, the recess is filled with conductive material. In such cases, steps of the staircase structure have a multilayer structure that includes an upper portion and a lower portion. The lower portion includes insulator material and the upper portion includes a layer of capacitor dielectric between first and second capacitor electrode plates, with the second capacitor electrode plates being continuous with, or otherwise in contact with, the conductive material in the recess.

Staircase-based metal-insulator-metal (MIM) capacitors

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts

Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprising germanium, silicon and boron that at least partially covers the epitaxial source or drain structures to provide low contact resistivity.

Reduced contact resistivity with PMOS germanium and silicon doped with boron gate all around transistors

Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.

Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology

Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

Source electrode and drain electrode protection for nanowire transistors

An integrated circuit structure includes a first non-planar semiconductor device and a second non-planar semiconductor device. The first non-planar semiconductor device includes a first body, a first gate structure at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body, a second gate structure at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height of the first body is at least 5% different from a second height of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.

Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation

Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi.

Integrated circuit structures including a titanium silicide material

A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Top gate recessed channel CMOS thin film transistor and methods of fabrication

A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Integration methods to fabricate internal spacers for nanowire devices

Techniques and mechanisms to impose stress on a transistor which includes a channel region and a source or drain region each in a fin structure. In an embodiment, a gate structure of the transistor extends over the fin structure, wherein a first spacer portion is at a sidewall of the gate structure and a second spacer portion adjoins the first spacer portion. Either or both of two features are present at or under respective bottom edges of the spacer portions. One of the features includes a line of discontinuity on the fin structure. The other feature includes a concentration of a dopant in the second spacer portion being greater than a concentration of the dopant in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer, wherein stress on the channel region is imposed at least in part with the buffer layer.

Device, method and system to provide a stressed channel of a transistor

Growing community of inventors

Portland, OR, United States of America

Anand S Murthy