Intel Corporation

Daedalus Prime LLC

Sony Group Corporation

Tahoe Research, Ltd.

Sony Corporation

Anand S Murthy

Tahir Ghani

Glenn A Glass

Jack T Kavalieros

Willy Rachmady

Gilbert W Dewey

Matthew V Metz

Chandra S Mohapatra

Harold W Kennel

Karthik Jambunathan

Cory C Bomberger

Robert S Chau

Sean T Ma

Daniel Bourne Aubertine

Cheng-Ying Huang

Biswajeet Guha

Seiyon Kim

Boyan Boyanov

Stephen M Cea

Kelin J Kuhn

Seung Hoon Sung

Ashish Agrawal

Nicholas G Minutillo

Benjamin Chu-Kung

Siddharth Chouksey

Ryan Keech

Brian S Doyle

Patrick R Morrow

Rishabh Mehandru

Anupama Bowonder

Rafael Rios

Abhijit Jayant Pethe

Roza Kotlyar

Mark T Bohr

Michael L Hattendorf

Mark Y Liu

Mark Armstrong

Cory E Weber

Suman Datta

Chia-Hong Jan

Mauro J Kobrinsky

Nadia M Rahhal-Orabi

Prashant Majhi

Wilfred Gomes

Nick Lindert

Paul A Packan

Abhishek A Sharma

Justin K Brask

Been-Yih Jin

Sanaz Kabehie Gardner

Shaofeng Yu

Subhash M Joshi

Nazila Haratipour

Kaizad Rumy Mistry

Aaron D Lilak

Bernhard Sell

Christopher J Jezewski

Annalisa Cappellani

Jun Sung Kang

Ravi Pillarisetty

Marko Radosavljevic

Van H Le

Niloy Mukherjee

Kimin Jun

Szuya S Liao

Ehren Mannebach

Richard E Green

Brian E Roberds

Jack Hwang

Steven J Keating

Dax M Crum

Pushkar Ranade

Aaron A Budrevich

Stephen T Chambers

Han Wui Then

Mark L Doczy

Anh Phan

Patrick H Keys

Justin R Weber

Gopinath Bhimarasetti

Arnab Sen Gupta

Pratik A Patel

Sansaptak W Dasgupta

Walid M Hafez

Debendra Mallik

Paul B Fischer

Omkar G Karhade

Ravindranath Vithal Mahajan

Nitin A Deshpande

Leonard P Guler

Huang-Lin Chao

Nicole K Thomas

Ebrahim Andideh

William Hsu

Joseph M Steigerwald

Mohit K Haran

Andy Chih-Hung Wei

Bruce E Beattie

Nancy M Zelick

Jenny Hu

Hybrid FETs and methods of forming such hybrid FETs are disclosed. An example hybrid FET includes a channel region, a first region, a second region, a third region, and two gates. A gate may wrap around a portion of the channel region. The channel region may be over a first substrate (e.g., a substrate on which the channel region is formed) but cross a second substrate. The channel region is shared by a MOSFET and a TFET. The first region and second region constitute the source and drain of the MOSFET and are doped with dopants of the same type. The first region and third region constitute the source and drain of the TFET and are doped with dopants of opposite types. The third region may be placed at the opposite side of the second substrate from the first region and the second region.

Field-effect transistor with hybrid switching mechanism

Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface co-planar with a top surface of the gate structure.

Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation

IC devices implementing 2T memory cells with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an 'angled transistor' if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. 2T memory cells with read and write transistors provided in different planes of an IC device, stacked substantially over one another, and having either the read transistors or the write transistors being angled transistors provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

Two transistor memory cells with angled transistors

Techniques are provided herein to form a semiconductor diode device within an integrated circuit. In an example, a diode device includes separate fins or bodies of semiconductor material that are separated by an insulating barrier. One of the fins or bodies is doped with n-type dopants while the other fin or body is doped with p-type dopants. Each of the first and second fins or bodies includes an epitaxially grown region over it that includes the corresponding dopant type with a higher dopant concentration. Additionally, each of the first and second fins or bodies includes another epitaxially grown region on the backside (e.g., under the fins or bodies) of the corresponding dopant type with a lower dopant concentration compared to the epitaxial regions on the opposite side of the fins or bodies. An undoped or lightly doped layer may also be formed between the epitaxially grown regions on the backside.

Diode structure with backside epitaxial growth

Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an 'angled transistor' if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

Memory arrays with backside components and angled transistors

Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm.

SiGe:GAB source or drain structures with low resistivity

Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

Package architecture of photonic system with vertically stacked dies having planarized edges

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a relatively high germanium content are described. In an example, an integrated circuit structure includes a fin including a semiconductor material. A gate stack is over an upper fin portion of the fin. A first epitaxial source or drain structure is embedded in the fin at a first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at a second side of the gate stack. The first and second epitaxial source or drain structures include silicon and germanium and have a same or greater atomic concentration of germanium than the fin.

Source or drain structures with relatively high germanium content

IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

Integrated circuit devices with angled transistors formed based on angled wafers

Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Integrated circuit structures having ultra-high conductivity global routing

Multi-plate MIM capacitors include a staircase structure, with steps including a high-k capacitor dielectric and one or more electrode plates. Contacts pass through insulator fill material and land on the electrode plate of a respective step. A recess passes through the staircase structure. In some examples, the recess is filled with insulator material, and steps of the staircase structure have a bilayer structure (e.g., lower layer of capacitor dielectric and upper layer of capacitor electrode plate). In other examples, the recess is filled with conductive material. In such cases, steps of the staircase structure have a multilayer structure that includes an upper portion and a lower portion. The lower portion includes insulator material and the upper portion includes a layer of capacitor dielectric between first and second capacitor electrode plates, with the second capacitor electrode plates being continuous with, or otherwise in contact with, the conductive material in the recess.

Staircase-based metal-insulator-metal (MIM) capacitors

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts

Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprising germanium, silicon and boron that at least partially covers the epitaxial source or drain structures to provide low contact resistivity.

Reduced contact resistivity with PMOS germanium and silicon doped with boron gate all around transistors

Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.

Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology

Growing community of inventors

Portland, OR, United States of America

Anand S Murthy