International Business Machines Corporation

An L Steegen

Ying Di Zhang

Cyril Cabral, Jr

Victor Ku

Haining S Yang

Vijay Narayanan

Ricky S Amos

Hsing-Jen C Wann

Clement Hsingjen Wann

Dureseti Chidambarrao

Christian Lavoie

Robert C Wong

Ying Li

Maheswaran Surendra

Jakub Tadeusz Kedzierski

John J Ellis-Monaghan

Oleg Gluschenkov

Zhijiong Luo

James Spiros Nakos

Huajie Chen

Sunfei Fang

Diane Catherine Boyd

Anda C Mocuta

Richard D Kaplan

Woo-Hyeong Lee

Chester T Dziobkowski

Franz X Zach

Evgeni Petrovich Gousev

Douglas A Buchanan

Maheswaren Surendra

Keith Kwong Hon Wong

Omer H Dokumaci

Yun-Yu Wang

Paul Charles Jamison

Kwong Hon Wong

Rajesh Rengarajan

Christopher V Baiocco

A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

Method and structure for forming strained SI for CMOS devices

A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

Selective silicon-on-insulator isolation structure and method

Method and structure for forming strained Si for CMOS devices

The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

CMOS silicide metal gate integration

A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.

Process options of forming silicided metal gates for advanced CMOS devices

A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

Method for forming self-aligned dual salicide in CMOS technologies

A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.

Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow

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Stamford, CT, United States of America

An L Steegen