Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

An-Chyi Wei

Ryan Chia-Jen Chen

Shu-Uei Jang

Chung-Shu Wu

Wei-Yeh Tang

Ya-Yi Tsai

Chien-Hua Tseng

Hang-Ting Lue

Erh-Kun Lai

Hong-Ji Lee

Shih-Ping Hong

Guan-Ru Lee

Yu-Wen Wang

Ta Hung Yang

Ying-Ya Hsu

Cheng-Yi Lung

A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Method for forming fin field effect transistor (FinFET) device structure

Method for forming fin field effect transistor (FinFet) device structure

A method of forming a semiconductor device includes removing a top portion of a dielectric layer surrounding a metal gate to form a recess in the dielectric layer; filling the recess with a capping structure; forming a patterned hard mask over the capping structure and over the metal gate, wherein a portion of the metal gate, a portion of the capping structure, and a portion of the dielectric layer are aligned vertically with an opening of the patterned hard mask; and performing an etch process on said portions of the metal gate, the capping structure, and the dielectric layer that are aligned vertically with the opening of the patterned hard mask, wherein the capping structure has an etch resistance higher than an etch resistance of the dielectric layer during the etch process.

Method of forming semiconductor device and semiconductor device

A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.

Method of forming semiconductor structure and semiconductor device

A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Fin field effect transistor (FinFET) device structure and method for forming the same

A method for forming a semiconductor device structure includes providing a substrate having a first fin structure and a second fin structure that are capped by a patterned hard mask structure. A liner layer and an overlying insulating layer are formed between the first and second fin structures. A multi-step etching process including a first step of selectively removing the patterned hard mask structure and a second step of in-situ and selectively removing a portion of the insulating layer to form an isolation feature is performed. The process gas used in the multi-step etching process includes a first etching gas and a second etching gas. The flow rate of the first etching gas is greater than that of the second etching gas in the first step and the flow rate of the first etching gas is less than that of the second etching gas in the second step.

A semi-damascene method is described for fabricating wordlines without stringers while maintaining critical cell dimensions when wordline pitch is less than 40 nm. A thin conducting layer protects a storage layer during manufacture, the thin conducting layer then making contact with filled-in conducting material.

Method of word-line formation by semi-damascene process with thin protective conductor layer

A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Semiconductor structure and manufacturing method of the same

Methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing Ngas and one or more process gases into the chamber; and etching the substrate, wherein the introduction of the Ngas is stopped prior to etching, and wherein etching comprises an initial plasma ignition wherein at least a portion of the Ngas remains present in the chamber during initial plasma ignition. Additional methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing Ngas and one or more process gases into the chamber; applying power to an electrode in the chamber such that an Nmemory species is formed; and etching the substrate, where the introduction of the Ngas into the chamber can be stopped prior to etching. Other methods are also described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing Ngas into the chamber; applying power to an electrode in the chamber such that an Nmemory species is formed; removing the applied power from the electrode in the chamber; stopping the introduction of the Ngas into the chamber and introducing one or more process gases into the chamber; and etching the substrate.

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Hsinchu, Taiwan

An-Chyi Wei