Taiwan Semiconductor Manufacturing Comp. Ltd.

Winbond Electronics Corporation

An-Chun Tu

Chen-Ming Huang

Chih-Jen Wu

Dun-Nian Yaung

Kuan-Chieh Huang

Chin-Hsiang Lin

Chun-Heng Chen

Jenn-Ming Huang

Chih-Hong Hwang

Yi Hsien Lu

Chen-Chien Li

Kuei-Shu Chang-Liao

Wen-Fa Tai

Tzu-Shih Yeu

Shih-Kuan Tai

A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes.

Semiconductor test structures

A method of forming a nitrogen-containing oxide film is disclosed. The method comprises (a) exposing a substrate to a first gas pulse having one of an oxygen-containing gas and a metal-containing gas; (b) exposing the substrate to a second gas pulse having the other of the oxygen-containing gas and the metal-containing gas to form an oxide film over the substrate; and (c) exposing the oxide film to a third gas pulse having a nitrogen-containing plasma to form a nitrogen-containing oxide film, wherein the nitrogen-containing oxide film has a nitrogen concentration between about 0.1 and about 3 atomic percent (at %).

Nitrogen-containing oxide film and method of forming the same

A method of making a backside illuminated image sensor includes forming a first isolation structure in a pixel region of a substrate, where a bottom of the first isolation structure is exposed at a back surface of the substrate. The method further includes forming a second isolation structure in a peripheral region of the substrate, where the second isolation structure has a depth less than a depth of the first isolation structure. Additionally, the method includes forming an implant region adjacent to at least a portion of sidewalls of the first isolation structure, where the portion of the sidewalls is located closer to the back surface than a front surface of the substrate, and where the second isolation structure is free of the implant region.

Method of making backside illuminated image sensors

A backside illuminated image sensor includes a substrate with a substrate depth, where the substrate includes a pixel region and a peripheral region. The substrate further includes a front surface and a back surface. The backside illuminated image sensor includes a first isolation structure formed in the pixel region of the substrate, where a bottom of the first isolation structure is exposed at the back surface of the substrate. The backside illuminated image sensor includes a second isolation structure formed in the peripheral region of the substrate, where the second isolation structure has a depth less than a depth of the first isolation structure. The backside illuminated image sensor includes an implant region adjacent to at least a portion of sidewalls of each isolation structure in the pixel region.

Backside illuminated image sensors and method of making the same

A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.

A backside illuminated image sensor includes an isolation structure passing through a substrate, a sensor element formed overlying the front surface of the substrate, and a color filter formed overlying the back surface of the substrate.

Isolation structure for backside illuminated image sensor

A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions.

Self-aligned static random access memory (SRAM) on metal gate

This description relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at the pixel contact hole area and performing contact filling. This description also relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes implanting N+ or P+ for pixel contact plugs at a pixel contact hole area, performing Physical Vapor Deposition (PVD) at pixel contact hole area, annealing for silicide formation at the pixel contact hole area, performing contact filling and depositing a first metal film layer, wherein the first metal film layer links contact holes for a source, a drain, or a poly gate of a CMOS device.

Method for reducing contact resistance of CMOS image sensor

A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; performing a plurality of processes to form a gate stack over the substrate, wherein the gate stack comprises a gate layer; measuring a grain size of the gate layer after at least one of the plurality of processes; determining whether the measured grain size is within a target range; and modifying a recipe of at least one of the plurality of processes if the measured grain size of the gate layer is not within the target range.

Advanced process control for gate profile control

A method for performing a CMOS Image Sensor (CIS) silicide process is provided to reduce pixel contact resistance. In one embodiment, the method comprises forming a Resist Protect Oxide (RPO) layer on the CIS, forming a Contact Etch Stop Layer (CESL), forming an Inter-Layer Dielectric (ILD) layer, performing contact lithography/etching, performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at pixel contact hole area, performing contact filling, and defining the first metal layer. The Resist Protect Oxide (RPO) layer can be formed without using a photo mask of Cell Resist Protect Oxide (CIRPO) photolithography for pixel array and/or without silicide process at pixel array. The method can include implanting N+ or P+ for pixel contact plugs at the pixel contact hole area. The contact filling can comprise depositing contact glue plugs and performing Chemical Mechanical Polishing (CMP).

A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source/drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.

Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios

A gas delivering device inside a gaseous reaction chamber capable of increasing gas flow in areas having a deficient supply of gas by forming additional holes in corresponding positions. Because a gas-delivering panel design having asymmetrical holes is employed, gas flow rate within the reactions chamber can be roughly balanced. Hence, a homogeneous stream of gaseous reactants can be maintained above the surface of a reacting wafer.

Gas delivering device

This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to both dual and single inverse copper damascene processes to form conducting copper interconnects and contact vias simultaneously, with low dielectric constant intermetal dielectrics (IMD). The low dielectric constant material, low-K, can be of four types of material: doped oxide, organic materials, highly fluorinated films, porous materials. In addition, spin-on glass (SOG) and spin-on-dielectric (SOD) are applicable. Key to the present invention are the following process steps, that have exceptionally advanced process controls: polysilicon etching of sacrificial polysilicon, plasma ashing of the patterning photoresist, and post cleaning. With conventional dual damascene, wherein dielectric material is patterned into dual damascene, several deleterious effects occur: (1) etching of low-K material can be difficult and can affect the electrical properties, (2) photoresist ashing can impact both the dielectric constant of low-K material and critical dimensional bias control, (3) post cleaning can impact the dielectric constant of low-K material. Using both the inverse dual and single damascene processes disclosed by this invention, the problems associated with convention damascene approaches are circumvented.

Growing community of inventors

Taipei, Taiwan

An-Chun Tu