Intel Corporation

Amram Eitan

Timothy A Gosselin

Shawna M Liff

Eric Jin Li

Nisha Ananthakrishnan

Yoshihiro Tomita

Robert M Nickerson

Dingying David Xu

Purushotham Kaushik Muthur Srinath

Shripad Gokhale

Mark Saltas

Elizabeth Nofen

Hsin-Yu Li

John Decker

Yang Guo

Nick Ross

Daewoong Suh

Yongki Min

Shankar Devasenathipathy

Joseph B Petrini

Hemanth K Dhavaleswarapu

Steven B Roach

Zhihua Li

George S Kostiew

Omkar G Karhade

Rahul N Manepalli

Nitin A Deshpande

Leonel R Arana

Edward Rudolph Prack

Rajendra C Dias

Steve S Cho

Xiaoying Guo

Changhua Liu

Elah Bozorg-Grayeli

Jung Kyu Han

Hongxia Feng

Tyler N Osborn

Danish Faruqui

Liwei Wang

Sivakumar Nagarajan

Lars D Skoglund

Zhaozhi Li

Peng Chen

Craig Jonathan Weinman

Venmathy McMahan

Kyle Mcelhinny

Amrita Mallik

Donglai David Lu

Anil R Indluru

Matthew T Magnavita

Kuang-Han Chu

Craig J Weinman

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates

Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone

An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.

Electronic assembly that includes a bridge

A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate

Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

Two material high K thermal encapsulant system

Introducing an underfill material over contact pads on a surface of an integrated circuit substrate; and ablating the introduced underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation. A method including first ablating an underfill material to expose an area of contact pads on a substrate using temporally coherent electromagnetic radiation; introducing a solder to the exposed area of the contact pads; and second ablating the underfill material using temporally coherent electromagnetic radiation. A method including introducing an underfill material over contact pads on a surface of an integrated circuit substrate; defining an opening in the underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation; introducing a solder material to the exposed area of the contact pads; and after introducing the solder, removing the sacrificial material.

Ablation method and recipe for wafer level underfill material patterning and removal

Embodiments of a thermal compression bonding (TCB) process cooling manifold, a TCB process system, and a method for TCB using the cooling manifold are disclosed. In some embodiments, the cooling manifold comprises a pre-mixing chamber that is separated from a mixing chamber by a baffle. The baffle may comprise at least one concentric pattern formed through the baffle such that the primary cooling fluid in the pre-mixing chamber is substantially evenly distributed to the mixing chamber. The pre-mixing chamber may be coupled to a source of primary cooling fluid. The mixing chamber may have an input configured to accept the primary cooling fluid and an output to output the primary cooling fluid.

Thermal compression bonding process cooling manifold

An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; and a porous coating that includes grains of metal powder formed onto the electronic component by melting the metal powder onto the electronic component. An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; and a porous coating that includes grains of metal powder formed onto the substrate by melting the metal powder onto the substrate. An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; an initial mold covering the electronic component; and a porous coating that includes grains of metal powder formed onto the initial mold by melting the metal powder onto the initial mold.

Electronic package that includes fine powder coating

The formation of electronic assemblies including a die having through vias is described. In one embodiment, a method includes providing Si die including a first surface and a second surface opposite the first surface, and forming a via extending through the Si die from the first surface to the second surface. The via is formed to have a larger width at the first surface than at the second surface, the larger width at the first surface being no less than 100 microns. The method also includes placing a plurality of particles in the via, wherein at least some of the particles comprise a polymer and at least some of the particles comprise a metal. The method also includes heating the die and the particles in the via to cross-link at least part of the polymer in the via, and cooling the die to solidify the polymer and form a electrically conductive composite including the cross-linked polymer and the metal in the via. Other embodiments are described and claimed.

In-situ formation of conductive filling material in through-silicon via

A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.

Microelectronic package interconnect and method of fabrication thereof

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Scottsdale, AZ, United States of America

Amram Eitan