Texas Instruments Corporation

Amitava Chatterjee

Seetharaman Sridhar

Alwin J Tsao

Sameer P Pendharkar

Mahalingam Nandakumar

Ih-Chin Chen

Xiaoju Wu

Shaoping Tang

Kayvan Sadra

Jong Shik Yoon

Theodore Warren Houston

Mark Stephen Rodder

Akram Ali Salman

Pinghai Hao

Imran Khan

Farzan Farbiz

Kaiping Liu

Somnath S Nag

Youngmin Kim

Iqbal Ali

Philipp Steinmann

Wei William Lee

Brian Edward Hornung

Maureen A Hanratty

Ping Yang

Greg A Hames

Charvaka Duvvury

Thomas L Polgreen

Manoj Mehrotra

Freidoon Mehrad

Richard A Chapman

Brian Goodlin

Keith Edmund Kunz

Purnendu K Mozumder

Kamel Benaissa

Vladimir Frank Drobny

Alec James Morton

Song Zhao

Xiang-Zheng Bo

Derek W Robinson

Ekanayake Ajith Amerasekera

Ajith E Amerasekera

Terry James Bordelon, Jr

Shirin Siddiqui

Qizhi He

Quzhi He

Syed Suhail Murtaza

Shian Aur

Zhiqiang (Jeff) Wu

Taylor R Efland

Haowen Bu

Howard L Tigelaar

Jiong-Ping Lu

David Barry Scott

Girish Anant Dixit

Shin-Puu Jeng

Rick L Wise

Kelly Jay Taylor

Craig Thomas Salling

Bernhard H Andresen

Hong Yang

Tathagata Chatterjee

Keith Alan Joyner

Hisashi Shichijo

Srinivasan Chakravarthi

Deborah J Riley

James R Hellums

Chin-Yu Tsai

Jeffrey A McKee

Lance Stanford Robertson

Duofeng Yue

E Ajith Amerasekera

Puneet Kohli

Doug Weiser

Steven E Marum

Sue E Crank

Manuel A Quevedo-Lopez

Donald S Miles

Victor C Sutcliffe

Roland Bucksch

Yin Hu

Peter S McAnally

P R Chidambaram

Jiann Liu

Karen H R Kirmse

Phillipp Steinmann

Jerry Che-Jen Hu

Sreedhar Natarajan

Suhail Murtaza

Terrence J Riley

Vivian Liu

Jerry C Hu

Agerico L Esquirel

A semiconductor controlled rectifier (FIG.A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region () having a first conductivity type (N) and a first heavily doped region () having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region () having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region () having the first conductivity type is formed within the second lightly doped region. A buried layer () having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region () having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region () having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

ESD protection circuit with isolated SCR for negative voltage operation

Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.

I-shaped gate electrode for improved sub-threshold MOSFET performance

Integrated circuits and manufacturing methods are presented for creating diffusion resistors () in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.

Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells

Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.

High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit

An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Drain extended CMOS with counter-doped drain extension

An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Low cost demos transistor with improved CHC immunity

An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

Deep collector vertical bipolar transistor with enhanced gain

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Plano, TX, United States of America

Amitava Chatterjee