Advanced Micro Devices Corporation

Spansion Llc.

Microsoft Technology Licensing, LLC

Globalfoundries Inc.

Amit P Marathe

Pin-Chin Connie Wang

Christy Mei-Chu Woo

Christine Hau-Riege

Steven C Avanzino

Minh Van Ngo

Hyeon-Seag Kim

Darrell M Erb

Connie Pin-Chin Wang

Van-Hung Pham

Nian Niles Yang

Matthew S Buynoski

Suzette Keefe Pangrle

Tien-Chun Yang

Hartmut Ruelke

Paul L King

Krishnashree Achuthan

John Sanchez

Kurt Taylor

Stefan Hau-Riege

Van Hung Pham

Kok Yong Yiang

Rick Francis

Bhanwar Singh

Ramkumar Subramanian

Fei Wang

Sergey D Lopatin

Calvin T Gabriel

Sunil D Mehta

Lu You

Brian K Langendorf

Luigi Capodieci

Kashmir S Sahota

Minh Quoc Tran

Xiao-yu Li

John Espinoza Sanchez, Jr

Nguyen Duc Bui

Diana M Schonauer

Kingsuk Maitra

Joffre F Bernard

Christy M-c Woo

Ercan Adem

Tung Thanh Nguyen

Young-chang Joo

Ranjit Gannamani

Rune Hartung Jensen

Rolf Geilenkeuser

Julia Purtell

Huade Walter Yao

Eugene Zhao

Seung-Hyun Rhee

Joerg-Oliver Weidner

Suzette K Prangrle

John Zhang

Embodiments are disclosed that relate to implementing semiconductor device cooling systems that leverage awareness of regional voltage and temperature reliability risk considerations. For example, one disclosed embodiment provides a method of implementing a cooling system configured to cool an integrated circuit. The method involves first determining a heat dissipation factor that would reduce each region of the integrated circuit to a reduced temperature in order to maintain an overall failure rate. An analysis is then performed, using an insight about the relative reliability risk of elevated voltage and temperatures, to identify a region of the integrated circuit whose temperature can be permitted to rise without exceeding the overall failure rate, thereby permitting implementation of a cooling system with a reduced heat dissipation factor.

Reliability aware thermal design

According to one exemplary embodiment, a non-destructive method for determining a breakdown voltage of a dielectric layer on a semiconductor substrate includes injecting a test current in increasing ramp steps into the dielectric layer. The method further includes measuring a test voltage across the dielectric layer at each increasing ramp step of the test current. The method further includes detecting a dropped test voltage in response to the increasing ramp steps of the test current. The ramp steps of the test current can be substantially logarithmically increased. The breakdown voltage of the dielectric layer can be designated to be substantially equal to the dropped test voltage.

Method and system for non-destructive determination of dielectric breakdown voltage in a semiconductor wafer

A time-to-breakdown for a dielectric layer in a semiconductor device is determined based upon a sudden change in capacitance. An alternating voltage, greater in magnitude than an operating voltage of the device, is applied to the semiconductor device, capacitance is measured across the dielectric layer during the application of the voltage until a sudden change in capacitance occurs, thereby indicating a breakdown in the dielectric layer, and the breakdown time is scaled to the operating voltage.

Dielectric breakdown lifetime enhancement using alternating current (AC) capacitance

A composite &#x3b1;-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a controlled surface roughness for improved adhesion, electromigration resistance and reliability. Embodiments include lining a damascene opening, such as a dual damascene opening in a low-k interlayer dielectric, with an initial layer of TaN, forming a graded tantalum nitride layer on the initial TaN layer and then forming an &#x3b1;-Ta layer on the graded TaN layer, the composite barrier layer having an average surface roughness (Ra) of about 25 &#x212b; to about 50 &#x212b;. Embodiments further include controlling the surface roughness of the composite barrier layer by varying the Nflow rate and/or ratio of the thickness of the combined &#x3b1;-Ta and graded tantalum nitride layers to the thickness of the initial TaN layer.

Composite barrier layers with controlled copper interface surface roughness

The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein the layout design tool creates an interconnect structure to satisfy electromigration criteria, and manipulating a design database within the design system.

Integrated circuit design system

Systems and methods are disclosed for testing semiconductors at the wafer level, specifically, systems and methods are disclosed that quantify line-edge roughness in terms of electrical properties and the impact of the line-edge roughness on device reliability and performance. A voltage ramp dielectric breakdown (VRDB) test is used to measure the breakdown voltage of the inter-digitated fingers of a semiconductor device. The distribution of breakdown voltage is used to measure the median breakdown voltage and the outliers which fan the extrinsic tail. Thereby, VRDB is used to quantify the impact LER will have on device reliability and performance. The systems and methods also provide a feedback tool to the fabrication process to control line edge roughness to a desired specification.

Quantifying and predicting the impact of line edge roughness on device reliability and performance

A method for efficiently and accurately measuring a maximum Vcalculation or failure rate and lifetime projection for microprocessors and other semiconductor products analytically scales low voltages applied to thinner oxides to thicker oxides. The expanded voltage window that is closer to the use voltage is obtained thereby to provide accurate voltage acceleration factors and max Vextraction.

Method for determining projected lifetime of semiconductor devices with analytical extension of stress voltage window by scaling of oxide thickness

A system that facilitates extraction of line edge roughness measurements that are independent of proprietorship of a metrology device comprises a structure patterned onto silicon with known line edge roughness values associated therewith. A metrology device obtains line edge roughness measurements from the structure, and a correcting component generates an inverse function based upon a comparison between the known line edge roughness values and the measured line edge roughness values. The metrology device can thereafter measure line edge roughness upon a second structure patterned on the silicon, and the inverse function can be applied to such measured line edge roughness values to enable obtainment of line edge roughness measurements that are independent of proprietorship of the metrology device.

Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures

Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via, and depositing memory element films. The improved Ta&#x2014;Cu interface of the subject invention mitigates and/or eliminates lateral growth of memory element films and copper voiding under the dielectric layer at the top surface of the metal line, and thereby enhances reliability and performance of semiconductor devices.

Use of Ta-capped metal line to improve formation of memory element films

For determining a failure characteristic of a semiconductor device, a leakage current characteristic is measured for the semiconductor device to determine a plurality of stress bias zones. A respective set of parameters that define a respective failure characteristic of the semiconductor device is determined for each of the stress bias zones such that the failure characteristic is accurately determined for a wide range of operating voltages.

Determination of device failure characteristic

Systems and methods are disclosed that facilitate predicting electromigration (EM) reliability in semiconductor wafers via decoupling intrinsic and extrinsic components of EM reliability. Electrical cross-sections of wafer test lines can be determined and individual currents can be forced through the test lines to force a constant current density across a test wafer. An EM reliability test can be performed to determine a purely intrinsic component of EM reliability. A single current can then be applied to all test lines and a second EM reliability test can be performed to determine total EM reliability. Standard deviations, or sigma, of failure distributions can be derived for each EM test. Intrinsic sigma can be subtracted from total sigma to yield an extrinsic sigma associated with process variation in wafer fabrication. Sigmas can then be utilized to predict EM reliability when process variations are adjusted, without application of a damaging package-level EM test.

Predicting EM reliability by decoupling extrinsic and intrinsic sigma

Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via to expose a portion of the metal line, and depositing memory element films. The improved Ta&#x2014;Cu interface of the subject invention mitigates and/or eliminates lateral growth of memory element films and copper voiding under the dielectric layer at the top surface of the metal line, and thereby enhances reliability and performance of semiconductor devices.

Method of forming composite barrier layers with controlled copper interface surface roughness

A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.

Semiconductor component and method for precluding stress-induced void formation in the semiconductor component

A composite &#x3b1;-Ta/ graded tantalum nitride /TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and reliability, reduced contact resistance, and increased process margin. Embodiments include a dual damascene structure in a low-k interlayer dielectric comprising Cu and a composite barrier layer comprising an initial layer of TaN on the low-k material, a graded layer of tantalum nitride on the initial TaN layer and a continuous &#x3b1;-Ta layer on the graded tantalum nitride layer. Embodiments include forming the initial TaN layer at a thickness sufficient to ensure deposition of &#x3b1;-Ta, e.g., as at a thickness of bout 50 &#x212b; to about 100 &#x212b;. Embodiments include composite barrier layers having a thickness ratio of &#x3b1;-Ta and graded tantalum nitride: initial TaN of about 2.5:1 to about 3.5:1 for improved electromigration resistance and wafer-to-wafer uniformity.

Cu interconnects with composite barrier layers for wafer-to-wafer uniformity

Growing community of inventors

Fremont, CA, United States of America

Amit P Marathe