Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Amit Kundu

Jaw-Juinn Horng

Yung-Chow Peng

Szu-Lin Liu

Chun-Wei Chang

Sheng-Feng Liu

Hsien Yu Tseng

Chung-Hui Chen

Yi-Hsiang Wang

Chia-Hsin Hu

Chung-Kai Lin

Shih-Cheng Yang

Yung-Shun Chen

A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.

Circuit, semiconductor device and method for parameter PSRR measurement

A device including delay cells connected in series and in a feedback loop to provide a ring oscillator. At least one of the delay cells in the ring oscillator is a stacked gate delay cell that includes two or more PMOS transistors having first drain/source paths connected in series to each other and having first gates connected to each other and two or more NMOS transistors having second drain/source paths connected in series to each other and to the first drain/source paths and having second gates connected to each other and to the first gates.

Low noise ring oscillator devices and methods

Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.

Voltage reference temperature compensation circuits and methods

An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Electromigration evaluation methodology with consideration of both self-heating and heat sink thermal effects

An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

A layout of a semiconductor device stored on a non-transitory computer-readable medium includes a first transistor in an active device region, the first transistor comprising a first channel region a first source region and a first drain region. The layout further includes a second transistor in a guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.

Heat sink layout designs for advanced FinFET integrated circuits

A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to the first AC component signal and the second AC component signal.

The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.

Temperature compensation circuits

A layout of a semiconductor device is stored on a non-transitory computer-readable medium. The layout includes a first transistor in an active device region and a second transistor in a guard ring region. The first transistor includes a first channel region, a first gate structure across the first channel region, and a first source region and a first drain region on opposite sides of the first channel region. The second transistor includes a second channel region, a second gate structure across the second channel region, a second source region and a second drain region on opposite sides of the second channel region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.

An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.

A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.

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Hsinchu, Taiwan

Amit Kundu