Samsung Electronics Co., Ltd.

Amit Berman

Ariel Doubchak

Evgeny Blaichman

Yaron Shany

Avner Dor

Uri Beitler

Dikla Shapiro

Elisha Halperin

Jun Jin Kong

Ron Golan

Tal Philosof

Sergey Gendel

Noam Livne

Yoav Shereshevski

Lior Kissos

Eli Haim

Lital Cohen

Idan Dekel

Junjin Kong

Elik Almog Sheffi

Dan Elbaz

Sarit Buzaglo

Alexander Bunin

Gari Fuks

Jonathan Zedaka

A storage system, including a host device; and a storage device including a nonvolatile memory and at least one processor configured to implement a storage internal protection (SIP) module, wherein the SIP module is configured to: obtain, from the host device, a plurality of storage commands corresponding to the nonvolatile memory, filter the plurality of storage commands to obtain a filtered plurality of storage commands, apply information about the filtered plurality of storage commands to a machine-learning cryptocurrency mining (CM) detection algorithm, and based on the machine-learning CM detection algorithm indicating that a CM operation is detected, provide a notification to the host device.

Anti-malware algorithm and HW/FW for internal SSD health and storage space protection against cyber-attacks

Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a plurality of data symbols; providing the plurality of data symbols to a neural network; obtaining a plurality of threshold voltage targets based on an output of the neural network; and programming the plurality of data symbols to a plurality of memory cells included in a storage device based on the plurality of threshold voltage targets.

Reviving faulty NAND by AI data modulation

A method for soft decoding of generalized Reed-Solomon (RS) error correction codes, includes receiving a codeword through a digital electronic communication channel; verifying that an HD error-and-erasures decoding has failed; finding a Groebner basis that accounts for a fixed set of erasures; constructing a Chase and GMD decoding tree on the set of Chase coordinates and the set of GMD coordinates; traversing the decoding tree using polynomials of the Groebner basis as a basis that represents updated coefficient polynomials on the Chase and GMD decoding tree; updating polynomials on the decoding tree using root and derivate steps that flip an edge, or a root step for an erasure edge; calculating error locations by polynomial evaluation of candidate polynomials from the decoding tree, and calculating error values by using Forney's formula; and correcting the received codeword according to the calculated error locations and calculated error values.

Fast combined chase and GMD decoding of generalized Reed-Solomon codes

Provided are a memory system, a method of reading data and a method of finding read thresholds. The method of finding read thresholds includes: selecting a channel distribution among a plurality of channel distributions that corresponds to a read page of the memory device to be read in response to a read command; generating a Trellis diagram based on a decoding scheme and a type of the read page; determining an optimal path through the Trellis diagram using the selected channel distribution according to a dynamic programming algorithm; and finding the read thresholds from the optimal path.

Setting optimal threshold voltages for reading data from a memory device based on a channel distribution

Systems, devices, and methods for encoding information bits for storage, including obtaining information bits; encoding the information bits using an inner code to obtain a plurality of inner code words; encoding the plurality of inner code words using an outer code to generate an outer code word; and storing the outer code word in a storage device, wherein at least one of the inner code and the outer code includes a generalized concatenated code (GCC), and wherein the outer code word includes a hierarchical-GCC (H-GCC) code word.

Generalized hierarchical concatenated codes with fixed dimension and code length

Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a frame corresponding to a codeword from the storage device, performing a first decoding operation on the frame, based on the first decoding operation indicating that a number of errors is greater than a predetermined number, selecting at least one potential error bit, and perform a second decoding operation based on the at least one potential error bit, based on the second decoding operation indicating that the number of errors is not equal to the predetermined number plus one, determining that the frame is not correctable by the first decoding operation and the second decoding operation, and based on the second decoding operation indicating that the number of errors is equal to the predetermined number plus one, correcting the frame based on a result of the second decoding operation to obtain a corrected frame, and obtaining information bits corresponding to the codeword based on the corrected frame.

High throughput polar codeword decoding by decoding bch sub-code in polar code structure

A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector αof soft information from a parent node; computing a vector αof soft information for a left child of node v; providing node v with a vector βof hard decisions from the left child and using it with αto create a soft information vector αand passing it to a right child of node v; providing node v with a vector βof hard decisions from its right child and using it with βto create a hard decision vector, βof hard decisions, and passing it to its parent node; updating, when v is a ileaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.

Acceleration of S-polar ECC throughput by scheduler

Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a codeword from among a plurality of codewords stored in a storage device, wherein the codeword includes a plurality of frames; obtaining an initial error locator polynomial (ELP) corresponding to the codeword; decoding a frame of the plurality of frames; based on determining that the frame is successfully decoded, determine an updated ELP based on the initial ELP and information about the frame; and obtaining information bits corresponding to the codeword based on the updated ELP, wherein the updated ELP includes a plurality of updated coefficients, and wherein the updated ELP is determined by simultaneously calculating at least two updated coefficients from among the plurality of updated coefficients.

Fast polynomial division by monomial for Reed-Solomon ELP maintenance

A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.

Encoding and decoding of data using generalized LDPC codes

A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Machine-learning error-correcting code controller

An storage device is provided. The storage device includes: a nonvolatile memory; and at least one processor configured to: obtain an input symbol to be stored in a target memory cell among a plurality of memory cells of the nonvolatile memory; obtain cell features of the plurality of memory cells; determine a target voltage for the target memory cell based on the input symbol and the cell features of the plurality of memory cells; and provide the target voltage to the target memory cell.

Programming by self adjusting program voltage targets compensating for cell-to-cell interference and PE cycles

Systems and methods of the present disclosure may be used to improve equalization module architectures for NAND cell read information. For example, embodiments of the present disclosure may provide for de-noising of NAND cell read information using a Multiple Shallow Threshold-Expert Machine Learning Models (MTM) equalizer. An MTM equalizer may include multiple shallow machine learning models, where each machine learning model is trained to specifically solve a classification task (e.g., a binary classification task) corresponding to a weak decision range between two possible read information values for a given NAND cell read operation. Accordingly, during inference, each read sample with a read value within a weak decision range is passed through a corresponding shallow machine learning model (e.g., a corresponding threshold expert) that is associated with (e.g., trained for) the particular weak decision range.

De-noising using multiple threshold-expert machine learning models

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.

ECC buffer reduction in a memory device

A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

Soft reed-solomon decoder for a non-volatile memory

A method, apparatus, non-transitory computer readable medium, and system for selecting program voltages for a memory device are described. Embodiments of the method, apparatus, non-transitory computer readable medium, and system may map a set of information bits to voltage levels of one or more memory cells based on a plurality of embedding parameters, program the set of information bits into the one or more memory cells based on the mapping, detect the voltage levels of the one or more memory cells to generate one or more detected voltage levels, and identify a set of predicted information bits based on the one or more detected voltage levels using a neural network comprising a plurality of network parameters, wherein the network parameters are trained together with the embedding parameters.

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Ramat Gan, Israel

Amit Berman