International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundries U.S. 2 LLC

Alvin Jose Joseph

Qizhi Liu

Alan Bernard Botula

Anthony K Stamper

James Albert Slinkman

Mark David Jaffe

James Stuart Dunn

Vibhor Jain

Robert Mark Rassel

Hanyi Ding

Siva P Adusumilli

Yun Shi

Jeffrey Bowman Johnson

David Louis Harame

Randy Lee Wolf

Peter B Gray

Ramsey M Hazbun

Steven M Shank

Michel J Abou-Khalil

Mark Levy

Edward J Nowak

John J Ellis-Monaghan

Richard A Phelps

Peter John Geiss

Marwan H Khater

John Joseph Pekarik

Xuefeng Liu

Renata A Camillo-Castillo

Zhong-Xiang He

Rajendran Krishnasamy

Max Gerald Levy

Ramana Murty Malladi

Bradley Alan Orner

Jeffrey P Gambino

Kathryn Turner Schonenberg

Andreas Daniel Stricker

Peter James Lindgren

David S Collins

Mete Erturk

Judson Robert Holt

Douglas Duane Coolbaugh

Wayne Harvey Woods, Jr

Michael Joseph Zierak

Theodore James Letavic

Alexander M Derrickson

Stephen Arthur St Onge

Cameron E Luce

Gerd Pfeiffer

James Randall Elliott

Christa Regina Willets

Kevin K Chan

Thomas N Adam

Edmund Juris Sprogis

Jagar Singh

Stephen Ellinwood Luce

Robert Allen Groves

Howard Smith Landis

David Charles Sheridan

Louis DeWolf Lanzerotti

Francois Pagette

Kimball M Watson

Dale Warner Martin

Dinh Dang

Erik Mattias Dahlstrom

Brett T Cucci

Beth Ann Rainey

Douglas Brian Hershberger

Brennan J Brown

John J Benoit

Wade J Hodge

Mark E Stidham

Devendra K Sadana

Brent A Anderson

Ping-Chuan Wang

James William Adkisson

Kirk David Peterson

Timothy Dooling Sullivan

Kai D Feng

Steven J Bentley

James Spiros Nakos

Ebenezer E Eshun

Vidhya Ramachandran

William James Taylor, Jr

Xiaojin Wei

Yves T Ngu

BethAnn Rainey

Russell T Herrin

Basanth Jagannathan

Jeonghyun Hwang

Mattias E Dahlstrom

Ryan Wayne Wuthrich

Raminderpal Singh

James J Quinlivan

Aaron Vallett

Ajay Raman

Alan D Norris

Donald J Papae

Pernell Dongmo

Blaine Jeffrey Gross

Dennis R Whittaker

Structures including a compound-semiconductor-based device and a silicon-based device integrated on a semiconductor substrate and methods of forming such structures. The structure includes a first semiconductor layer having a top surface and a faceted surface that fully surrounds the top surface. The top surface has a first surface normal, and the faceted surface has a second surface normal that is inclined relative to the first surface normal. A layer stack that includes second semiconductor layers is positioned on the faceted surface of the first semiconductor layer. Each of the second semiconductor layers contains a compound semiconductor material. A silicon-based device is located on the top surface of the first semiconductor layer, and a compound-semiconductor-based device is located on the layer stack.

Integration of compound-semiconductor-based devices and silicon-based devices

The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

Switches in bulk substrate

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

Bipolar transistor with stepped emitter

Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

Semiconductor structure with semiconductor-on-insulator region and method

Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

Integrated circuit structure with through-metal through-substrate interconnect and method

The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

Photodetector with buried airgap reflectors

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.

Field-effect transistors with a crystalline body embedded in a trench isolation region

Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.

Lateral bipolar transistor structure with superlattice layer and method to form same

A semiconductor structure is provided. The semiconductor structure comprises a heat generating device arranged over a substrate. An interlayer dielectric (ILD) material may be arranged over the heat generating device and the substrate. A metallization layer may be arranged over the interlayer dielectric material. A thermal shunt structure may be arranged proximal the heat generating device, whereby an upper portion of the thermal shunt structure may be arranged in the interlayer dielectric material and may be lower than the metallization layer, and a lower portion of the thermal shunt structure may be arranged in the substrate.

Semiconductor structure having a thermal shunt below a metallization layer and integration schemes

Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

Lateral bipolar junction transistor including a stress layer and method

Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

Field-effect transistors with a body pedestal

Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

Semiconductor device structures with a substrate biasing scheme

The present disclosure relates to semiconductor structures and, more particularly, to lateral bipolar transistors and methods of manufacture. The structure includes: an extrinsic base comprising semiconductor material; an intrinsic base comprising semiconductor material which is located below the extrinsic base; a polysilicon emitter on a first side of the extrinsic base; a raised collector on a second side of the extrinsic base; and sidewall spacers on the extrinsic base which separate the extrinsic base from the polysilicon emitter and the raised collector.

Lateral bipolar transistors with polysilicon terminals

A semiconductor device is provided, the semiconductor device comprising a substrate having merged cavities in the substrate. An active region is over the merged cavities in the substrate. A thermally conductive layer is in the merged cavities in the substrate, whereby the thermally conductive layer at least partially fills up the merged cavities in the substrate. A first contact pillar connects the thermally conductive layer in the merged cavities in the substrate with a metallization layer above the active region.

Substrate with a buried conductor under an active region for enhanced thermal conductivity and RF shielding

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Williston, VT, United States of America

Alvin Jose Joseph