Intel Corporation

Sandisk 3d LLC

Matrix Semiconductor, Inc.

Sandisk Technologies Inc.

Alper Ilkbahar

Roy E Scheuerlein

Luca Giovanni Fasoli

Andrew J Walker

Derek Bosch

Sucheta Nallamothu

En-Hsing Chen

Sanjay Dabral

Mark G Johnson

Harry Muljono

Bendik Kleveland

J James Tringali

Pablo Martin Rodriguez

Christopher John Petti

Tanmay Kumar

Tak Ming Mak

Kedar Patel

Dilip K Sampath

Bruce Woolery

Christopher John Sine

Igor Koutnetsov

Ian A Young

Er-Xuan Ping

Stefan Rusu

Thomas H Lee

April Dawn Schricker

Timothy J Maloney

Christopher S Moore

Simon M Tam

Matthew P Crowley

David N Harris

James Nadir

Kent R Townley

Sunny C Huang

David Russell Friedman

R Tim Frodsham

Ching-Hua Chu

Mike J Tripp

Scott W Murray

Colm P Lysaght

Jason C Stinson

Christopher Cheng

Pablo M Rodriguez

April D Shricker

A volatile resistive memory device includes a resistive memory element including a barrier material portion and a charge-modulated resistive memory material portion. The barrier material portion includes a material selected from germanium and a silicon-germanium alloy, and the charge-modulated resistive memory material portion includes a non-filamentary, electrically conductive metal oxide. The resistive memory device may be a volatile eDRAM device. In operation, reading a resistance state of the resistive memory element does not disturb the resistance state of the charge-modulated resistive memory material portion.

Volatile memory device employing a resistive memory element

A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

Three-dimensional memory device incorporating segmented array line memory array

In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.

Memory cell that includes a carbon-based memory element and methods of forming the same

In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.

A method of making a nonvolatile memory cell includes forming a steering element and forming a carbon resistivity switching material storage element by coating a carbon containing colloid.

Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing

A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.

Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4Fmemory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.

Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.

System architecture and method for three-dimensional memory

Three-dimensional memory device incorporating segmented bit line memory array

The preferred embodiments described herein provide a memory device and method for redundancy/self-repair. In one preferred embodiment, a memory device is provided comprising a primary block of memory cells and a redundant block of memory cells. In response to an error in writing to the primary block, a flag is stored in a set of memory cells allocated to the primary block, and the redundant block is written into. In another preferred embodiment, an error in writing to a primary block is detected while an attempt is made to write to that block. In response to the error, the redundant block is written into. In yet another preferred embodiment, a memory device is provided comprising a three-dimensional memory array and redundancy circuitry. In still another preferred embodiment, a method for testing a memory array is provided. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Memory device and method for redundancy/self-repair

An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

Semiconductor device with localized charge storage dielectric and method of making same

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San Jose, CA, United States of America

Alper Ilkbahar