National Semiconductor Corporation

Alon Shacham

Rami Saban

Avner Efendovich

Varda Karpati

Peleg Lior

Donald B Alpert

Gideon Intrater

Oved Oz

Yomtov Sidl

Yomtov Sidi

A testability architecture and method for loosely integrated (modularized) integrated circuits uses stand alone module testing. For an integrated circuit chip which has a number of independent modules, where one module design is used in a number of different chips, each module is connected to the chip's input/output pins and to a configuration module. To make testing of the modules more efficient and less expensive, during testing of the chip a particular module design is confronted with the same testing environment regardless of the actual chip in which it is present. Advantageously, chip area is only slightly enlarged by the test circuitry. A test architecture of the configuration module includes test registers and carries out a standard protocol for all read and write transactions during testing. This approach provides better test coverage and economizes in test generation.

Testability architecture for modularized integrated circuits

Testability method for modularized integrated circuits

The data separator of this invention may be used for extracting clock and data signals from a serial stream of bits read from a magnetic disk or tape. The data separator is supplied with a 'fast' clock pulse generated by a frequency multiplexer. After a lock indication from the frequency multiplier, during the first eight serial data pulses the frequency and phase of the data separator are synchronized to the serial data pulses. Then an early and late logic unit keeps track digitally of the cumulative phase difference between the incoming data stream and the output of the data separator. When the cumulative phase difference reaches predetermined limits, the phase of the output is adjusted. If a second phase adjustment is required in the same direction (i.e., early or late), the frequency of the output is adjusted. The output of the data separator is generated by a decrementing register, the phase or frequency of the data separator being adjusted by increasing or decreasing the initial value loaded into the decrementing register. The data separator is fully digital.

Fully digital data separator and frequency multiplier

A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.

Selectively locking memory locations within a microprocessor's on-chip

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Tel Aviv, Israel

Alon Shacham