Advanced Micro Devices Corporation

Alline F Myers

Paul Raymond Besser

Sergey D Lopatin

Jeremias D Romero

Matthew S Buynoski

Steven C Avanzino

Lu You

Suzette Keefe Pangrle

Pin-Chin Connie Wang

Darrell M Erb

Minh Quoc Tran

Robert Matthew Ulfig

Phin-Chin Connie Wang

An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition

A method for measuring porosity of nanoporous materials is provided using atomic force microscopy (AFM). A surface topology map with sub-atomic resolution is created using AFM wherein the pore shape and size can be determined by measuring the pores that intersect the top or fracture surface. For porous materials requiring more accurate measurements, small scan areas with slow scan speed and fine AFM tips are used and a general estimation on distribution can be made from a sample area.

Method for determining pore characteristics in porous materials

A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.

Method of inserting alloy elements to reduce copper diffusion and bulk diffusion

An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. Before planarization of the conductor core and the barrier layer, an anneal of the semiconductor substrate is performed at high temperatures of 400&deg; C. and above to stimulate grain growth. After planarization, subsequent high temperature deposition of passivating or capping layers will not cause grain growth and hillocks will be suppressed.

Anneal hillock suppression method in integrated circuit interconnects

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Santa Clara, CA, United States of America

Alline F Myers