Teradyne, Inc.

Allan M Ryan

Ronald A Sartschev

Eric David Blom

Ernest P Walker

Andrew W Kittross

The invention is directed to techniques for providing a test procedure for testing a device using automatic test equipment (ATE). An ATE system includes memory having a test application stored therein, a test interface to connect to the device, and a processor coupled to the memory and the test interface. The processor is configured to operate in accordance with the test application to (i) provide a series of instructions based on a test procedure defining a device testing task, and (ii) control the test interface based on the provided series of instructions in order to test the device. The test procedure includes multiple test elements. Each test element defines instructions and programmable input variables that direct the processor to perform a particular test operation of the device testing task. The user of the ATE system combines test elements when creating the test procedure rather than write code from scratch, or modify code of prewritten templates. Accordingly, the user does not need to possess knowledge of a programming language or low-level ATE component details.

Easy to program automatic test equipment

Pin slice circuitry used in automatic test equipment is disclosed. The pin slice circuitry includes a portion implemented using CMOS technology and a portion implemented using bipolar technology. The CMOS portion includes a plurality of timing generator circuits, digital sigma delta modulator circuitry used to generate digital bit streams representative of analog reference levels, and programmable digital signal processing circuitry. The bipolar portion includes driver/receiver channels, a parametric measurement unit, and decoder circuitry, which produces the analog reference levels from the digital bit streams generated by the modulator circuitry. The analog reference levels are used by the driver/receiver channels and the parametric measurement unit; and, the digital signal processing circuitry is used to monitor and control levels produced by the parametric measurement unit. The disclosed pin slice circuitry has the advantages of reduced size and cost as compared with conventional pin slice circuitry.

Low-cost configuration for monitoring and controlling parametric measurement units in automatic test equipment

Pin slice circuitry used in automatic test equipment is disclosed. The pin slice circuitry includes a portion implemented using CMOS technology and a portion implemented using bipolar technology. The CMOS portion includes a plurality of timing generator circuits and sigma delta modulator circuitry, which is used to generate digital bit streams representative of analog reference levels. The bipolar portion includes driver/receiver channels, a parametric measurement unit, and decoder circuitry, which produces the analog reference levels from the digital bit streams generated by the modulator circuitry. The analog reference levels are used by the driver/receiver channels and the parametric measurement unit. The disclosed pin slice circuitry has the advantages of reduced size and cost as compared with conventional pin slice circuitry.

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Billerica, MA, United States of America

Allan M Ryan