Intel Corporation

Intel Ndtm US LLC

Micron Technology Incorporated

Sk Hynix Nand Product Solutions Corp.

Aliasgar S Madraswala

Yogesh B Wakchaure

Xin Guo

Sagar Upadhyay

Purval Shyam Sule

Kristopher H Gaewsky

Pranav Kalavade

David J Pelster

Ali Khakifirooz

David B Carlton

Trupti Bemalkhedkar

Naveen Vittal Prabhu

Naveen Prabhu Vittal Prabhu

Shantanu R Rajwade

Shankar Natarajan

Donia Sebastian

Neelesh Vemula

Camila Jaramillo

Rohit Sudhir Shenoy

Feng Zhu

Mark Anthony Golez

Bharat M Pathak

Karthikeyan Ramamurthi

Simon Ramage

Wayne D Tran

Pranav Chava

Bhaskar Venkataramaiah

Lei Chen

Dheeraj Srinivasan

Myron Loewen

Matthew Goldman

Charan Srinivasan

Ryan J Norton

Brennan A Watt

Pratyush Chandrapati

Netra Mahuli

Nehul N Tailor

Sungho Park

Heonwook Kim

Sagar S Sidhpura

Varsha Regulapati

Naga Kiranmayee Upadhyayula

Quan H Ngo

Leonard Aaron Turcios

Violante Moschiano

Krishna Kumar Parat

Richard M Fastow

Michele Incarnati

Walter Di Francesco

Anand S Ramalingam

Uday Chandrasekhar

Ye Zhang

Suresh Nagarajan

Rezaul Haque

Yu Du

Arun Sitaram Athreya

Binh N Ngo

Xin Sun

Curtis A Gittens

Yihua Zhang

Antonino Giuseppe La Spina

Sriram Balasubrahmanyam

Eric L Hoffman

Nathan Chrisman

Binh Ngo

Darshak A Udeshi

Ahsanur Rahman

John Egler

Cole Uhlman

Joel T Jorgensen

Shanmathi Mookiah

Bharat Pathak

Siddhanth Munukutla

Tanya Wanchoo

Jiantao Zhou

Sandeep Rasoori

Archana Tankasala

Sanket Sanjay Wadyalkar

Vinaya Harish

Karthi Ramamurthi

Fei Xue

Bhavya Lokasani

Kevin P Flanagan

Manjiri M Katmore

Renjie Chen

Jong Tai Park

NAND performance is increased by reducing the time to perform program operations. An operation to program a portion of NAND cells in a NAND memory array includes multiple stages. NAND performance is increased by reducing the time in a first stage of the multiple stages to compute parameters that are used in a second stage to perform program operation(s) and verify operation(s). The time in the first stage is reduced by enabling dynamic prologue selection to dynamically select one of multiple sets of first stage operations to be performed in the first stage for a program operation based on the Word Line (WL), WL-Group, and block information for a current program operation and a previous program operation.

Method and apparatus to reduce time to program single level cell blocks in a non-volatile memory

Methods and apparatus for Enhanced IO Interface for PLC program and program-suspend-resume operations. A NAND memory device includes blocks of single-level cell (SLC) memory and multi-level cell (MLC) memory storing n-bits per cell such as quad-level cell (QLC) or penta-level cell (PLC) memory. The NAND memory device further includes a plurality of page buffer latches and logic to copy data from a set of n SLC pages in a block of SLC memory into n respective page buffer latches and copy data from the respective page buffer latches to an MLC page (e.g., QLC or PLC page) in a block of MLC memory. These operations can be extended for NAND memory devices having multiple planes with blocks of SLC and QLC/PLC memory. QLC/PLC program and program-resume operations are supported with optional ECC correction operations.

Enhanced IO interface for plc program and program-suspend-resume operations

A storage device includes a storage array with multiple planes organized as plane groups, where the planes of a plane group receive and process commands in parallel. The storage device includes a storage controller that receives a command from a host controller. In response to receipt of the command the storage controller provides ready information for all planes to the host controller. The multiple planes can optionally have independent multiplane read operation (IMPRO). Each plane group can have a first plane and a second plane, and the storage controller can optionally read data from the first plane of a plane group in response to a virtual ready signal for the first plane, before the second plane of the plane group is ready.

Express status operation for storage devices with independent planes and plane groups

Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.

Lean command sequence for multi-plane read operations

A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Solid state drive with multiplexed internal channel access during program data transfers

The size of page map memory in a NAND flash device used to store page related information is decreased by embedding page type in a row address. The row address is received by the NAND flash device from the host on the data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during the row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array. A same block segment number is used for each page type in the block segment.

Method and apparatus to reduce memory in a NAND flash device to store page related information

Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.

Independent multi-page read operation enhancement technology

For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

Smart prologue for nonvolatile memory program operation

Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (L1) of the MLC memory.

Dynamic program caching

Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.

Dynamic gate steps for last-level programming to improve write performance

Skip program verify for dynamic start voltage (DSV) sampling reduces latency of a program operation on multi-level cell (MLC) memory having at least two pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND device. The NAND device skips program verifies corresponding to higher levels of voltage thresholds during DSV sampling. As a result, the NAND device can reduce a total program time (tPROG) to program the MLC memory, and determine the dynamic start program voltage more quickly. The NAND device can improve an effective TLC NAND tPROG by as much as 2% without impacting the placement of the first sub-block being programmed. The skipped program verifies corresponding to the higher levels of voltage thresholds are resumed as soon as DSV sampling is complete.

Skip program verify for dynamic start voltage sampling

Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.

Block list management for wordline start voltage

A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a 'sticky voltage') for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.

Method and apparatus to improve read latency of a multi-threshold level cell block-based non-volatile memory

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

Persistent data structure to track and manage SSD defects

Growing community of inventors

Folsom, CA, United States of America

Aliasgar S Madraswala