Intel Corporation

Microsoft Technology Licensing, LLC

Facebook, Inc.

Other

Uber Technologies, Inc.

Ali-Reza Adl-Tabatabai

Bratin Saha

Gad Shlomo Sheaffer

Jan Stephen Gray

Tatiana Shpeisman

David S Callahan

Quinn Able Jacobson

Martin Taillefer

Yang Ni

Vadim Bassin

Guei-Yuan Lueh

Richard Lewis Hudson

Anwar Ghuloum

Guilherme De Lima Ottoni

Vijay Menon

Adam Welc

Vinod Grover

Burton Jordan Smith

Michael H Paleczny

Dave Detlefs

Hong Wang

Cheng C Wang

Youfeng Wu

Arun Upadhyaya Kishan

Koichi Yamada

Landy Wang

Yosseff Levanoni

Brian Murphy

Ben J Ashbaugh

Sreenivas Subramoney

Rajkishore Barik

Mauricio J Serrano

Michael M Magruder

Tomasz Janczak

Chris J Newburn

Gilles A Pokam

Cristiano L Pereira

Jayanth N Rao

Ram Huggahalli

Jeffrey V Olivier

James Henry Cownie

Kshitij Arun Doshi

Justin E Gottschlich

Per H Hammarlund

Haitham H Akkary

Gautham N Chinya

John Thomas Shen

Matthew C Merten

Ravi Rajwar

John P Shen

Herbert H J Hum

Shiliang Hu

Robert Geva

Jayashankar Bharadwaj

Darek Josip Mihocka

Ethan Schuchman

Suresh Srinivas

Dhaval Patel

Ady Tal

Yossi Levanoni

Ben Hertzberg

Sion Berkowits

Moshe Maury Bach

Anne Weinberger Bracy

Mike Magruder

Masoud Saeida Ardekani

Matt Tolton

Denis Haenikel

Balaji Varadarajan

Simon Santiago Soriano-Perez

Sundaram Ananthanarayanan

Altug Koker

Shlomo Raikin

Xinmin Tian

Wei-Yu Chen

Keith Adams

Robert L Farrell

Mohan Rajagopalan

Peter Lachner

Ara Victor Nefian

Jinzhan Peng

Zhiwei Ying

Hariharan L Thantry

Richard Wurdack

Ravi Narayanaswamy

Leaf Petersen

Konstantin Stanislavovich Bobrovsky

Bratin Saba

Adam Wele

Serguei V Preis

Vyacheslav Pavlovich Shakin

Victor Ying

David Callahn

Graefe Goetz

Sreevinas Subramoney

Cheng Wang

A green master is maintained in a code repository. A code management system receives changes to the code and maintains an ordered revision queue. A hierarchical set of builds is defined with each build corresponding to a code change. A model is applied to determine a value for each build, with the value being based on the probability that the build will ultimately be used. A build schedule is determined based on the values for the builds and at least some of the builds are implemented to determine whether committing the corresponding code changes keep the master green or not. Code changes that keep master green are committed to the code repository.

Scalable code repository with green master

Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

Methods and systems to identify and reproduce concurrency violations in multi-threaded programs using expressions

A method and apparatus for optimizing quiescence in a transactional memory system is herein described. Non-ordering transactions, such as read-only transactions, transactions that do not access non-transactional data, and write-buffering hardware transactions, are identified. Quiescence in weak atomicity software transactional memory (STM) systems is optimized through selective application of quiescence. As a result, transactions may be decoupled from dependency on quiescing/waiting on previous non-ordering transaction to increase parallelization and reduce inefficiency based on serialization of transactions.

Optimizing quiescence in a software transactional memory (STM) system

A system for optimizing cache coherence message traffic volume is disclosed. The system includes a plurality of caches in a multi-level memory hierarchy and a plurality of agents. Each agent is associated with a cache. The system includes one or more monitoring engines. Each agent in the plurality of agents is associated with a monitoring engine. The agents can execute a processor level software instruction causing a memory region to be private to the agent. Each of the agents is configured to execute a memory access for data on an associated cache and to send a request for data up the hierarchy on a cache miss. The monitoring engine is configured to intercept request for data from an agent and to prevent snooping for the cache line in peer caches when the cache line associated with a memory region represented as private to the agent.

Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache hierarchy

Disclosed here are methods, systems, paradigms and structures for optimizing intermediate representation (IR) of a script code for fast path execution. A fast path is typically a path that handles most commonly occurring tasks more efficiently than less commonly occurring ones which are handled by slow paths. The less commonly occurring tasks may include uncommon cases, error handling, and other anomalies. The IR includes checkpoints which evaluate to two possible values resulting in either a fast path or slow path execution. The IR is optimized for fast path execution by regenerating a checkpoint as a labeled checkpoint. The code in the portion of the IR following the checkpoint is optimized assuming the checkpoint evaluates to a value resulting in fast path. The code for handling situations where the checkpoint evaluates to a value resulting in slow path is transferred to a portion of the IR identified by the label.

Optimizing intermediate representation of script code for fast path execution

Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.

Efficient garbage collection and exception handling in a hardware accelerated transactional memory system

A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Method and apparatus to facilitate shared pointers in a heterogeneous platform

A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced.

Hardware acceleration of a write-buffering software transactional memory

A memory race recorder (MRR) is provided. The MRR includes a multi-core processor having a relaxed memory consistency model, an extension to the multi-core processor, the extension to store chunks, the chunk having a chunk size (CS) and an instruction count (IC), and a plurality of cores to execute instructions. The plurality of cores executes load/store instructions to/from a store buffer (STB) and a simulated memory to store the value when the value is not in the STB. The oldest value in the STB is transferred to the simulated memory when the IC is equal to zero and the CS is greater than zero. The MRR logs a trace entry comprising the CS, the IC, and a global timestamp, the global timestamp proving a total order across all logged chunks.

Tracing mechanism for recording shared memory interleavings on multi-core processors

Disclosed here are methods, systems, paradigms and structures for incrementally compiling scripts at runtime to generate executable code. The incremental compilation generates executable code corresponding to basic blocks of a script in various phases and at various scopes. In a first phase, an executable code for a basic block of the script is generated for a set of types of variables of the basic block. The generated executable block is stored and executed for subsequent requests. In a second phase, a set of executable blocks whose profiling information, such as frequency of (a) execution, (b) transition between two executable blocks, or (c) execution of a particular path, satisfies an optimization criterion is identified. The identified set of executable blocks are combined to generate an executable control region, which is more optimal than the executable blocks generated in the first phase. The executable control region is executed for subsequent requests.

Enlarging control regions to optimize script code compilation

In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode

Disclosed here are methods, systems, paradigms and structures for optimizing generation of intermediate representation (IR) for a script code by eliminating redundant object reference count operations from the IR. An IR of the script includes (a) a set of first code that increments a reference count of an object when a programming construct refers to the object, and (b) an associated set of second code which decrements the reference count of the object when a reference to the object is removed. The IR is analyzed to identify a subset of the set of second code which, upon execution, does not decrement the reference count of the object to a zero value. The subset of second code and the first code corresponding to the subset is removed from the IR to generate an optimized IR. The optimized IR is further converted to an executable code.

Optimizing intermediate representation of script code by eliminating redundant reference count operations

A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.

Hybrid linear validation algorithm for software transactional memory (STM) systems

Disclosed here are methods, systems, paradigms and structures for optimizing intermediate representation (IR) of a script code for atomic execution. Atomic execution of the script is achieved by generating portions of the IR as an atomic transaction. In an atomic transaction, a series of operations either all execute, or none executes. The IR includes checkpoints that evaluate to one of two possible values. The checkpoint evaluates to a first value when there is no error during execution, and evaluates to a second value when an error occurs. The IR is optimized for atomic execution by regenerating a portion of the IR including the checkpoint and code associated with the checkpoint as a transaction. When an error occurs during the execution of the transaction, the transaction is aborted and a state of execution of the script code is reverted to a state prior to the beginning of the transaction.

Optimizing intermediate representation of script code for atomic execution

Growing community of inventors

Santa Clara, CA, United States of America

Ali-Reza Adl-Tabatabai