Micron Technology Incorporated

Ali Feiz Zarrin Ghalam

Qiang Tang

Eric N Lee

Luigi Pilolli

Guan Wang

Kaveh Shakeri

Hoon Choi

Agatino Massimo Maccarrone

Daesik Song

Chin Yu Chen

Toru Tanzawa

Yoav Weinberg

Xiaojiang Guo

Dean K Nobunaga

Leonid Minz

Myung Gyoo Won

Chin-Yu Chen

Jongin Kim

Ramin Ghodsi

Xiangyu Tang

Daniel J Hubbard

Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.

Data burst queue management

Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.

Data burst suspend mode using pause detection

A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

Data burst suspend mode using multi-level signaling

Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

Systems and methods involving write training to improve data valid windows

An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

Data bus duty cycle distortion compensation

A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.

Write training in memory devices by adjusting delays based on data patterns

A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

Wave pipeline including synchronous stage

Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

Level shifter with reduced duty cycle variation

A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.

Wave pipeline

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

Internal clock distortion calibration using DC component offset of clock signal

Write training in memory devices

A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage between a data input node and a data output node. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The clock path includes a plurality of clock stages corresponding to the plurality of wave pipeline data stages between an input clock node and a return clock node. Each clock stage has a delay configured to be equal to a delay of the corresponding wave pipeline data stage. The wave pipeline includes a second data latch to latch the data on the data output node in response to a return clock signal on the return clock node. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

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Sunnyvale, CA, United States of America

Ali Feiz Zarrin Ghalam