International Business Machines Corporation

Credence Systems Corporation

Algirdas J Gruodis

Dale E Hoffman

Philip Theodore Kuglin

John Balyoz

Kurt Paul Szabo

Teh-Sen Jen

Daniel E Skooglund

Charles A Puntar

John E Dickol

Wadie Faltas Mikhail

Philip George Emma

Scott Barnett Swaney

Ferenc Miklos Bozso

Albert Y Chang

Yiu-Hing Chan

Lawrence Joseph Grasso

Michael L Combs

Mark L Shulman

Hans P Muhlfeld

David Patrick Hillerud

Carroll E Morgan

Piyushkumar C Patel

Badih John Rask

Yihua E Chang

Charles W Rodriguez

Yi-Hua E Chang

Dinh L Do

A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR) supplied as input thereto. An instruction processor receives each instruction read out of the instruction memory and alters the address input to the instruction memory in accordance with the received instruction so that the instruction memory reads out a next instruction. The instruction processor, which includes a conventional return address stack, is capable of executing conventional address increment, call and return instructions. The instruction processor is also capable of executing a temporary return instruction (TEMP) by incrementing its current address output to produce a new return address, by setting its address output to the value of a return address previously saved in the stack, by popping the saved return address from the stack, and by pushing the new return address onto the stack. Temporary return instructions enable instruction program flow to pass back and forth between a main program and a called subroutine.

Instruction processing pattern generator controlling an integrated

An integrated circuit (IC) tester organizes an IC test into a succession of test cycles, each test cycle being subdivided into four segments. The tester includes a separate tester channel for carrying out a test activity at each IC pin during each segment of the test cycle. The tester also includes a separate pattern generator for each channel. Each pattern generator concurrently generates four vectors at the start of each test cycle. Each vector tells the channel what activity it is to carry out during a separate segment of the test cycle. Each pattern generator includes a low-speed vector memory storing large blocks of vectors at each address and a cache memory system for caching blocks of vectors read out of the vector memory at a low frequency and then reading vectors out in sets of 16 at the higher test cycle frequency. A vector alignment circuit selects from among the cache memory output vectors to provide the four vectors to the channel for the test cycle. Thus the frequency of test activities carried out by the tester is four times greater than the cache memory read access frequency and many times the vector memory read access frequency. To conserve vector memory space when repetitive vector sequences are to be generated, the cache memory system repeatedly read accesses various vector sequences both in the vector memory and in the cache memory.

Algorithmic pattern generator for integrated circuit tester

An algorithmic pattern generator produces an output data value during each cycle of a clock signal. The pattern generator includes an addressable instruction memory reading out an instruction during each clock signal cycle. A memory controller normally increments the instruction memory's address during each clock signal cycle, but may jump to another address N+1 clock signal cycles after receiving a CALL, RETURN, REPEAT or BRANCH command from an instruction processor. The instruction processor normally executes the instruction read out of the instruction memory during each clock signal cycle and provides a data field included in the executed instruction as the pattern generator's output data. Other fields of the instruction reference a command the instruction processor sends to the memory controller. Since the memory controller requires N+1 clock signal cycles to respond to a command, it continues to increment the instruction memory address for N clock signal cycles after receiving the command before it actually performs an address jump. Instead of the N instructions read out of instruction memory during the N clock signal cycles after sending a jump command, the instruction processor executes an appropriate set of N instructions pre-loaded into an auxiliary buffer memory. During the next clock signal pulse thereafter, when the memory controller has had time to make the address jump, the instruction processor resumes executing instructions read out of the instruction memory.

Algorithmic pattern generator

A method for making a processor system immune to circuit failure caused by external noise using mirrored processors, and a recovery unit integral with the method, are disclosed. Identical addresses and data information is generated in each of two processors. The data is then partitioned into registers and Error Correction Codes (ECC's) are generated for the data. The address, data, and ECC information for each processor is then interlaced in a data structure. The interlaced structures of each processor are then compared. If the comparison yields no errors, the data is checkpointed in the recovery unit; if an error is detected, a recovery sequence can be initiated after the check-stop operation, whereby the system is restored to the last error-free checkpointing operation.

Recovery unit for mirrored processors

A parallel operation linear feedback shift-register (LFSR) that generates random test patterns or creates a signature that represents the response of a device under test at ultra high speed using low speed components and/or a slow rate clock. The apparatus is comprised of: a register connected to an external clock, and a plurality of combinatorial logic networks sequentially connected, the last of which drives the register which in turn feeds back into the first of the combinatorial logic networks. Each of the combinatorial networks provides a pseudo-random pattern which are then outputted in parallel, thereby creating a high speed data flow. By providing additional data inputs to the combinatorial networks, the pseudo-random patterns become the signature of the input data.

Parallel operation linear feedback shift register

A method, and apparatus for accomplishing the method, for controlling an operation of a test pin of a per-pin semiconductor device test system. The method includes the steps of, during a test cycle, generating a plurality of timing signals, providing a test pattern comprised of M-bits, and decoding the M-bits into one of 2.sup.M first multi-bit control words. In accordance with logical states of bits of the first control word, the method selects specified ones of the timing signals and generates a stimulus signal at a test pin in accordance with the selected specified ones of the timing signals. In accordance with an aspect of the invention, the step of providing provides test patterns at a rate of (x) test patterns per second, the step of generating generates test pin stimulus signals at a rate of (y) stimulus signals per second, and wherein (y)=n(x), where (n) is an integer greater than one.

Per pin circuit test system having N-bit pin interface providing speed

A programmable pulse generator that uses high resolution programmable delay circuits (HRPDCs) as building blocks, each of which is capable of changing timing 'on-the-fly', i.e., modifying the programmable delay within one tester cycle and without the limitations of existing delay circuits. The pulse generator comprises a timing control array that is subdivided into three components providing coarse delay, fine delay and extra-fine delay; a plurality of timing generators respectively controlled by the timing control array, each generator further comprising a plurality of HRPDCs, programmable delay circuits, and fixed delay blocks appropriately combined to modify pulse delay and pulse edges within each cycle.

High resolution programmable pulse generator employing controllable delay

An Algorithmic Test Pattern Generator (APG) of sufficient simplicity to be replicated at every pin of a tester. This APG is comprised of two counters and various controls capable of manipulating the counters and generating output data which is based on command and counter status. The circuit is capable of testing VLSI logic and analog circuitry, and is specifically well suited to test embedded arrays that can only be accessed through LSSD shift register chains.

Test pattern generator for testing embedded arrays

Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2.sup.M or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin. The test system also includes test pin signal receiving circuitry [26] for coupling to the test pin for receiving an electrical signal therefrom. Other predetermined ones of the control bits are coupled to the receiving circuitry for specifying, for each of the test cycles, at least one operating characteristic associated with the receiving circuitry.

Per-pin integrated circuit test system having n-bit interface

A driver circuit is disclosed for use in testing bi-directional transceiver semiconductor products using a minimum of time and number of product accessing pins. The driver includes a pair of controllable amplitude current sources whose output currents are selectably switched into or partially away from the commonly connected emitters of a current switch. The current switch is energized by a variable voltage source and produces the output test voltage.

Driver circuit for testing bi-directional transceiver semiconductor

Disclosed is a method and circuit for reducing and maintaining constant overshoot in a high speed driver. The circuit includes a predriver circuit which is driven single endedly and a driver circuit which is differentially driven by the predriver outputs. The predriver and the driver are differential pairs, with commonly controlled individual transistor current sources. A diode has been added in series with each emitter of the differential pairs. Schottky diodes are preferable because of their low capacitance. The diodes increase the input switching voltage (the smallest input voltage swing that will cause the outputs to fully switch) of the differential pair because they must also be switched on and off. The increase results in an increase in effective transition time, which results in smaller overshoots because the circuit is being switched slower. The output amplitude of the driver is set by a voltage which controls the current source currents of the commonly controlled current sources. As the amplitude is decreased the input switching voltage decreases because the current through the devices decreases which results in smaller base-emitter and diode voltages. Due to the commonly controlled current sources, the predriver amplitude decreases as the driver amplitude decreases. The predriver is designed such that its variable output supplies the driver with the proper input switching voltage at any driver amplitude. This keeps the effective input transition time constant which results in constant output overshoot.

Apparatus for reducing and maintaining constant overshoot in a high

An array testing apparatus includes a plurality of pin pattern generators for individually generating serial bit sequences required at each pin of a device under test during the testing operation. The individual pin pattern generators receive starting addresses from one or more programmable controllers and each pin pattern generator then performs a subroutine to repeat basic patterns or combinations of basic patterns as necessary. Both the pin pattern generators and the programmable controllers may include loop logic for obtaining the desired repetition sequences.

Distributed pattern generator

A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest-order end of the counter, can be selectively inhibited to effectively vary the cycle period of the counter. The digital word with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment of the phase of the output timing pulse stream is effected by a controllable phase-locked loop.

High-speed programmable timing generator

An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

High density semiconductor circuit layout

An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor in a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical geometric form and arranged in columnar arrays.

Growing community of inventors

Wappingers Falls, NY, United States of America

Algirdas J Gruodis