Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Alfred Haeusler

Jeffrey A Babcock

Angelo Pinto

Gregory Eric Howard

Scott G Balster

Scott Balster

Badih El-Kareh

Philipp Steinmann

Christoph Dirnecker

Vladimir Frank Drobny

Manfred Schiekofer

Wolfgang Heinz Schwartz

Michael Schober

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer () beneath the gate dielectric () and source and drain regions () of a MOS transistor. The carbon containing layer () will prevent the diffusion of dopants into the region () directly beneath the gate dielectric layer ().

Advanced CMOS using super steep retrograde wells

A fully embedded micromechanical device and a system on chip is manufactured on an SOI-substrate. The micromechanical device comprises a moveable component having a laterally extending upper and lower surface and vertical side surfaces. The upper surface is adjacent to an upper gap which laterally extends over at least a part of the upper surface and results from the removal of a shallow trench insulation material. The lower surface is adjacent to a lower gap which laterally extends over at least a part of the lower surface and results from the removal of the buried silicon oxide layer. The side surfaces of the movable component are adjacent to side gaps which surround at least a part of the vertical side surfaces of the moveable component and result from the removal of a deep trench insulation material.

Fully embedded micromechanical device, system on chip and method for manufacturing the same

A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped.

Semiconductor device including a deep contact and a method of manufacturing such a device

A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the active layer so as to generate an area having an increased doping concentration in the bulk substrate at the interface between the bulk substrate and the insulating layer.

Tuning of SOI substrate doping

A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer.

Method of manufacturing an electronic device including a PNP bipolar transistor

A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.

Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer

In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.

Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor

A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.

Growing community of inventors

Freising, Germany

Alfred Haeusler