Stmicroelectronics S.r.l.

Alfio Guarnera

Mario Giuseppe Saggio

Edoardo Zanetti

Leonardo Fragapane

Cristina Tringali

Simone Rascuna'

Ferruccio Frisina

Angelo Magri'

Simone Rascuna′

Francesco Lizio

Claudio Chibbaro

Simone Rascuná

Cateno Marco Camalleri

Alessia Maria Frazzetto

An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

4H-SiC electronic device with improved short-circuit performances, and manufacturing method thereof

A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

Manufacturing method of a semiconductor device with efficient edge structure

A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

Silicon carbide vertical conduction MOSFET device for power applications and manufacturing process thereof

A vertical-conduction MOSFET device formed in a body of silicon carbide having a first and a second face and a peripheral zone. A drain region, of a first conductivity type, extends in the body between the two faces. A body region, of a second conductivity type, extends in the body from the first face, and a source region, having the first conductivity type, extends to the inside of the body region from the first face of the body. An insulated gate region extends on the first face of the body and comprises a gate conductive region. An annular connection region, of conductive material, is formed within a surface edge structure extending on the first face of the body, in the peripheral zone. The gate conductive region and the annular connection region are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.

Vertical-conduction silicon carbide MOSFET device having improved gate biasing structure and manufacturing process thereof

An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

Silicon carbide power device with improved robustness and corresponding manufacturing process

4H&#x2014;SiC electronic device with improved short-circuit performances, and manufacturing method thereof

A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.

4H-SiC MOSFET device and manufacturing method thereof

An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:&#x2014;an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;&#x2014;an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.

Power MOSFET comprising a plurality of columnar structures defining the charge balancing region

An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

Process for manufacturing a power semiconductor device having charge-balance columnar structures on a non-planar surface, and corresponding power semiconductor device

An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.

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Trecastagni, Italy

Alfio Guarnera