Texas Instruments Corporation

National Semiconductor Corporation

Alexei Sadovnikov

Jeffrey A Babcock

Natalia Lavrovskaya

Binghua Hu

Andrew Derek Strachan

Peter J Hopper

Vladislav Vashchenko

Henry Litzmann Edwards

Richard Wendell Foote, Jr

Pushpa Mahalingam

Sheldon Douglas Haynie

Umamaheswari Aghoram

Mohamed N Darwish

Reda R Razouk

Guruvayurappan Mathur

Gang Xue

Sameer P Pendharkar

William David French

Peter B Johnson

Akram Ali Salman

Abbas Ali

Andy Strachan

Joel Martin Halbert

Guru Mathur

Stefan Herzer

Jamal Ramdani

Mattias E Dahlstrom

Doug Weiser

Eugene C Davis

Monir H El-Diwany

Scott Kelly Montgomery

Dening Wang

Yanbiao Pan

Ujwal Radhakrishna

Punit Bhola

Christopher Boguslaw Kocon

Mahalingam Nandakumar

Xiaoju Wu

James Robert Todd

Erika Lynn Mazotti

Zia Alan Shafi

Martin B Mollat

Terry Lee Lines

Saurabh Desai

Christopher John Knorr

Joseph Anthony DeSantis

Dhanoop Varghese

Edward F Pressley

Christoher J Knorr

Clint Alan Naquin

Jarvis Benjamin Jacobs

Richard Wendell Foote

An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter.

LOCOS fillet for drain reduced breakdown in high voltage transistors

A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

Vertical deep trench and deep trench island based deep n-type well diode and diode triggered protection device

A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

Rugged LDMOS with field plate

Described examples include an integrated circuit having a transistor with a first gate on a first gate insulating layer. The transistor also has second gate separated from the first gate by a gate gap. The integrated circuit also includes a channel well at the gate gap extending under the first gate and the second gate. The transistor has a first source in the channel adjacent to an edge of the first gate. The transistor having a second source formed in the channel adjacent to an edge of the second gate separated from the first source by a channel gap. The transistor has at least one back-gate contact, the at least one back-gate contact separated from the first gate by a first back-gate contact gap and separated from the second gate by a second back-gate contact gap.

Laterally diffused metal-oxide semiconductor (LDMOS) transistor with integrated back-gate

A method of manufacturing an integrated circuit includes forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer and has a second conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

False collectors and guard rings for semiconductor devices

A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

Semiconductor doped region with biased isolated members

A microelectronic device including an analog MOS transistor. The analog transistor has a body well having a first conductivity type in a semiconductor material of a substrate of the microelectronic device. The body well extends deeper in the substrate than a field relief dielectric layer at the top surface of the semiconductor material. The analog transistor has a drain well and a source well having a second, opposite, conductivity type in the semiconductor material, both contacting the body well. The drain well and the source well extend deeper in the substrate than the field relief dielectric layer. The analog transistor has a gate on a gate dielectric layer over the body well. The drain well and the source well extend partway under the gate at the top surface of the semiconductor material.

Low cost, high performance analog metal oxide semiconductor transistor

An integrated circuit chip and a method of fabricating the IC chip to include a transistor having a thick gate oxide in combination with STI. The method provides a wafer for which a source region location, a drain contact region location, an extended drain region location and a gate region location have been defined and forms an STI structure overlying the extended drain region location. After growing a gate oxide layer over the gate region location and a portion of the extended drain region location, the method forms a gate structure on the gate oxide layer, the gate structure having a gap overlying the intersection of an edge of the STI structure with the gate oxide layer.

DMOS transistor having thick gate oxide and STI and method of fabricating

A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.

Carbon, nitrogen and/or fluorine co-implants for low resistance transistors

A method includes implanting dopant of a first conductivity type into an epitaxial layer of semiconductor material to form first and second false collector regions adjacent to the surface of the epitaxial layer. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer from dopant of a second conductivity type that is opposite the first conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

An integrated circuit includes a transistor that has an collector region, a base region laterally surrounded by the collector region, and an emitter region laterally surrounded by the base region. A silicide layer on the emitter region is laterally spaced apart from the base region by an unsilicided ring. The emitter region is laterally spaced apart from a base contact region that may be covered by a dielectric layer such as a gate oxide layer.

Transistor having an emitter region with a silicide spaced apart from a base contact

A semiconductor device includes a bipolar junction transistor having a collector, a base, and an emitter. The collector includes a current collection region, a constriction region laterally adjacent to the current collection region, and a contact region laterally adjacent to the constriction region, located opposite from the current collection region. The current collection region, the constriction region laterally, and the contact region all have the same conductivity type. The base includes a current transmission region contacting the current collection region and a constricting well laterally adjacent to, and contacting, the current transmission region and contacting the constriction region. The current transmission region and the constricting well have an opposite conductivity type than the current collection region, the constriction region laterally, and the contact region.

Bipolar junction transistor with constricted collector region having high gain and early voltage product

A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

MOS transistor with folded channel and folded drift region

Growing community of inventors

Sunnyvale, CA, United States of America

Alexei Sadovnikov