Silicon Wafer Technologies, Inc.

Other

Alexander Yuri Usenko

William Ned Carr

Alexander Ulyashin

A process for making silicon on insulator wafer by bond and etch back—BESOI. A boron etch stop is formed by BF2+ ion implantation followed by solid phase epitaxy—SPE. Fluorine getters metals for OISF immunity of the final wafer. SPE activates boron above solubility limit thus facilitates high etch selectivity. Future cap silicon film is epitaxially grown over the boron etch stop at temperature that limits boron diffusion and boron deactivation. High temperature hydrogen bake step in epitaxy is replaced with Siconi of similar low temperature process. Buried oxide is thermally grown from portion of cap silicon layer at temperature limiting Boron diffusion and deactivation. Thus, SOI wafer design is the same as in layer transfer process—bonding interface is at the bottom interface of BOX; properties of final SOI wafer are equal to SOI made by layer transfer process—including cap silicon layer thickness variation, and OISF defect count. Advantage over the layer transfer—this process does not require non-standard equipment. Standard processing tool set readily available at semiconductor foundries is sufficient to run this process. Foundries can use this process for in house SOI wafer manufacturing.

Method of making a silicon on insulator wafer

A process for making silicon on insulator wafer by bond and etch back&#x2014;BESOI. Fluorine ion implantation is performed after bonding and after removal of etch stop layers. The ion energy is chosen to have a peak of ion distribution near the wafer bonding interface. The ion dose is chosen to exceed silicon amorphization threshold at maximum ion distribution. The ion dose is chosen low enough to keep silicon surface crystalline. Solid phase epitaxy SPE is performed after the implant. Finalizing of wafer bonding is performed after the SPE by anneal at 800 C. SPE is performed by anneal where temperature is slow ramped up from 450 to 600 C. In further chipmaking process, defect generation as oxidation induced stacking faults&#x2014;OISFs&#x2014;during oxidation step is prevented. OISF are not generated even in metal contaminated wafers. As process does not includes high temperature anneal, RF SOI devices&#x2014;like front chips of smartphones&#x2014;made on these wafers have advanced RF performance. Process uses only standard equipment readily available at semiconductor foundries; therefore, the process can be easily implemented at foundries.

Silicon-on-insulator wafer and low temperature method to make thereof

A process for preparing a surface of an optical article to improve light reflection and light transmission properties while conserving mechanical properties as durability and scratch resistance of the surface. A blank film is deposited on a base article. The film is post processed to convert a flat surface into near close packed array of near hemispherical protuberances. The conversion done in 2 steps. First the film is scratched to honeycomb pattern. Second the article is annealed. The anneal causes sequential transformation of flat film into the array. The transformation starts from scratch lines and go to a center of each honeycomb island cell. It is driven by dewetting phenomena. Characteristic size of the protuberances is controlled by initial film thickness. For low reflectivity of visible light, the initial blanket film is near 150 nm thick.

Method of making a surface with improved mechanical and optical properties

Process for forming a fragile layer inside of a single crystalline substrate near one of the substrate surfaces. The fragile layer is created by collecting hydrogen in high concentration at a desired depth. The hydrogen layer is collected on a seed layer. The seed layer is formed by ion implantation of non-doping species and annealing. The implantation introduces defects that are capable to trap hydrogen, and annealing confines the seed layer making it flat and thin. Then protium hydrogen ions are implanted at elevated temperature. The protium implantation depth is bigger than the depth of the seed layer. The implanted protium moves to the seed layer and trap there. The process is useful for making silicon-on-insulator (SOI) wafers. SOI with an ultrathin superficial silicon layer of high quality can be obtained. Hydrogen can be implanted at high dose rate, and thus the SOI wafers can be manufactured with high throughput and low cost. SOI wafers also have high quality as superficial silicon does not contain microvoids.

Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers

Process for forming a fragile layer inside of a single crystalline substrate near one of the substrate surfaces. The fragile layer contains hydrogen mostly in form of hydrogen platelets oriented in parallel to each other and to neighboring crystal surface. The fragile layer is preferably grown within a single crystalline silicon wafer to facilitate the detachment of an overlaying thin layer of single crystalline silicon from the initial wafer. The hydrogen layer is grown on a seed layer. The seed layer is preferably formed by ion implantation of inert gases at doses in 10cmrange. The hydrogen layer is grown by plasma hydrogenation of the substrate. The hydrogenation process begins at substrate temperature not exceeding 250&#xb0; C., and than continues at higher temperature not exceeding 400&#xb0; C. The method can be used to fabricate silicon-on-insulator (SOI) wafers wherein a thin layer of single crystalline silicon is detached from a silicon substrate along the fragile layer and attached to a substrate with an insulator on top of that substrate.

Process for forming a fragile layer inside of a single crystalline substrate

The invention provides a method of making silicon-on-insulator SOI substrates with nitride buried insulator layer by implantation of molecular deuterated ammonia ions ND, instead of implanting nitrogen ions (N, or N) as is done in prior art nitride SOI processes. The resultant structure, after annealing, has a buried insulator with a defect density which is substantially lower than in prior art nitride SOI. The deuterated nitride SOI substrates allow much better heat dissipation than SOI with a silicon dioxide buried insulator. These substrates can be used for manufacturing of high speed and high power dissipation monolithic integrated circuits.

Method of making starting material for chip fabrication comprising a buried silicon nitride layer

A technique for forming a film of crystalline material, preferably silicon. The technique creates a sandwich structure with a weakened region at a selected depth underneath the surface. The weakened region is a layer of porous silicon with high porosity. The high porosity enclosed layer is formed by (1) forming a porous silicon layer with low porosity on surface of the substrate, (2) epitaxial growth of a non-porous layer over the low-porous layer (3) increasing of porosity of the low-porous layer making the said layer hi-porous, (4) cleaving the semiconductor substrate at said high porous layer. The porosity of the buried low-porous layer is increased by hydrogenation techniques, for example, by processing in hydrogen plasma. The process is preferentially used to produce silicon-on-insulator wafers.

Method of producing a thin layer of crystalline material

A process for producing a multilayered substrate. In a first step, an adhesive layer is applied to a surface of a support substrate. Then a device substrate is placed into contact with the adhesive surface. Then the adhesive is cured. Then the device substrate is thinned. The device substrate has a hydrogen trap layer inside. The trap layer is formed by ion implantation through a face surface of the device substrate. The adhesive is chosen from compounds that release hydrogen upon curing. Thinning of the device substrate is performed by cleavage along a fragile layer of hydrogen microbubbles. The microbubble layer is formed through gettering of hydrogen released from the adhesive layer upon curing onto the trap layer and evolving the trapped hydrogen into the microbubbles. The substrates are preferably silicon single crystalline wafers and the adhesive is preferably hydrogen-silsesquioxane. The process is preferentially used to manufacture silicon-on-adhesive wafers for microelectromechanical systems, multilayer CMOS, and optoelectronic applications. The layered wafers have one or more thin single crystalline device layers and one or more sacrificial/spacer layer.

Method of manufacture of a multi-layered substrate with a thin single crystalline layer and a versatile sacrificial layer

A process for manufacturing a silicon-on-insulator wafer from a silicon wafer assembly. The assembly is made of two wafers. One of the wafers contains a fragile layer. The fragile layer is a layer containing a high amount of hydrogen. An amount of energy from an energy source is applied to the assembly to separate the assembly along the fragile layer thus forming a silicon-on-insulator wafer and a leftover wafer. The energy source is selected from the group consisting of: ultrasound, infrared, hydrostatic pressure, hydrodynamic pressure, or mechanical energy. The amount of energy is chosen to be sufficient to transform the fragile layer into a quasi-continuous gaseous layer. Under separation the hydrogen-enriched layer transforms into layer consisting of hydrogen platelets and hydrogen microbubbles.

Separation process for silicon-on-insulator wafer fabrication

A process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate from thermally oxidized silicon wafer so that processing temperatures are limited to 900&deg; C. is disclosed. The substrate is fabricated using H split process. Processing temperatures are limited to temperature of initiating of out-diffusion of oxygen from silicon dioxide into silicon. The limit prevents deterioration of buried oxide, and the oxide has low hole trap density that is equal to the trap density of an initial thermal silicon dioxide. Processing temperatures after implantation for H split process are limited to temperature of stability of dislocation microloops induced by the implantation at its damage peak. Resulting SOI structure have a gettering layer made from the microloops. The getter prevents yield drop caused by heavy metal contamination during the fabrication. Finished SOI devices have improved gate oxide integrity. Also, finished SOI circuitry has suppressed hot-electron controlled effects (backgating, transistor threshold voltage stability, side leakage). Also, radiation hardness of finished SOI devices is higher then the hardness of the SOI devices fabricated by conventional methods.

Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate

A method for forming ICs comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon. In accordance with one embodiment of the method, the entire semiconductor substrate with at least partially prefabricated semiconductor devices disposed thereon is subjected to irradiation sufficient to impart high resistance throughout the substrate and active semiconductor layer. A thin, low resistance, active semiconductor layer is then generated on the substrate body by localized annealing. The (partially) prefabricated semiconductor devices are restored to operability by virtue of the annealing step as defects in the top insulating layers and properties of thin layers underneath the insulator-semiconductor interfaces are &ldquo;healed.&rdquo; The annealing step does not, however, heal the defects in the bulk substrate so that it remains semi-insulating. The localized annealing step of the present invention is facilitated as a result of the difference in the thermal stability of radiation-induced defects in the bulk substrate and in the interface regions. Resultant semiconductor integrated circuits have decreased parasitic capacitances, decreased cross-talk, increased radiation hardness, suppressed latch-up, and improved speed action.

Method for forming IC's comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon

Process for lift-off of a thin layer from a crystalline substrate, preferably the layer from a silicon wafer to further form a silicon-on-insulator (SOI) sandwich structure, wherein a separative interlayer comprises a thin quasi-continuous gaseous layer and said interlayer is obtained by gettering a monatomic hydrogen into a preformed buried defect-rich layer preferably obtained by implantation. The monatomic hydrogen is preferably inserted into the substrate by electrolytic means.

Process for lift-off of a layer from a substrate

The method of the invention causes fracture of a semiconductor layer containing semiconductor devices from a support layer and requires no masking of the semiconductor device features during an implantation action. The method initially implants protons throughout an entirety of the semiconductor layer at an energy level that enables the protons to reach a depth that defines a delamination region. The implanting creating defects in the semiconductor devices and charge accumulation in dielectric portions (if any). Next a heat treating step causes a delamination of the semiconductor layer from the support layer that lies beneath the delamination region. Then the semiconductor layer is annealed at a temperature that exceeds a thermal stability temperature of the defects to cause a healing thereof.

Process for lift off and transfer of semiconductor devices onto an alien substrate

A method for fabricating MEMS wherein a structural member is released without using a sacrificial layer. In one embodiment, the method comprises forming a buried hydrogen-rich layer in a semiconductor substrate, defining a release structure in the semiconductor substrate above the buried hydrogen-rich layer, and separating at least a portion of the release structure from the semiconductor substrate by cleaving the semiconductor substrate at the buried hydrogen-rich layer. The method can be used to fabricate hybrid devices wherein a MEMS device and a semiconductor device are formed on the same chip.

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Murray Hill, NJ, United States of America

Alexander Yuri Usenko