General Electric Company

Cree Gmbh

Semiconductor Components Industries, LLC

University of South Carolina

Abb Schweiz Ag

Alexander Viktorovich Bolotnikov

Peter Almern Losee

Reza Ghandi

David Alan Lilienfeld

Victor Mario Torres

Kevin Sean Matocha

Ljubisa Dragoljub Stevanovic

Avinash Srikrishnan Kashyap

Anant Kumar Agarwal

Qingchun Zhang

Richard J Saia

Thomas Bert Gorczyca

Stephen Daley Arthur

Michael J Hartig

Stacey Joy Kennerly

Tangali S Sudarshan

James William Kretchmer

Yang Sui

Ahmed Elasser

Peter Micah Sandvik

Alvaro Jorge Mari Curbelo

Richard Alfred Beaupre

Ramakrishna Rao

Zachary Matthew Stum

Alexey V Vert

Kuna Venkat Satya Rama Kishore

James Jay McMahon

Stanislav Ivanovich Soloviev

Fabio Carastro

Fredrik Allerstam

Peter Almem Losee

Gregory Thomas Dunne

Joe Walter Kirstein

Richard Joseph Saia

Kuna Venkat Kishore

James Jay Mcmahon

In some aspects, the techniques described herein relate to a diode including: a substrate of a first conductivity type; a semiconductor layer of the first conductivity type disposed on the substrate, the semiconductor layer including a drift region; a shield region of a second conductivity type disposed in the semiconductor layer adjacent to the drift region; a surface region of the first conductivity type disposed in a first portion of the drift region adjacent to the shield region, the surface region having a doping concentration that is greater than a doping concentration of a second portion of the drift region adjacent to the surface region, the second portion of the drift region excluding the surface region; and a Schottky material disposed on: at least a portion of the shield region; the surface region in the first portion of the drift region; and the second portion of the drift region.

Diodes with schottky contact including localized surface regions

A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

Techniques for fabricating charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) devices

A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

Systems and methods for junction termination of wide band gap super-junction power devices

The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.

Systems and methods for junction termination in semiconductor devices

A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.

Systems and methods for unipolar charge balanced semiconductor power devices

Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.

Techniques for fabricating planar charge balanced (CB) metal-oxide-semiconductor field-effect transistor (MOSFET) devices

Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

Semiconductor device and method of making thereof

A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.

Systems and methods for integrated diode field-effect transistor semiconductor devices

A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC&#x2014;CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.

Systems and methods for termination in silicon carbide charge balance power devices

The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells using body region extensions

To manufacture a super-junction (SJ) layer of a SJ device, an epitaxial (epi) layer having a first conductivity type may be formed on an underlying layer, which may be formed from a wide-bandgap material. A first mask may then be formed onto a first portion of the epi layer, and a first set of SJ pillars may be selectively implanted into a second portion of the epi layer exposed by the first mask. Then, a second mask may be formed on the second portion of the epi layer that is self-aligned relative to the first mask. After removing the first mask, a second set of SJ pillars may be selectively implanted into the first portion of the epi layer. Removing the second mask may then yield the SJ layer.

Super-junction semiconductor device fabrication

An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (&#x3bc;m).

High energy ion implantation for junction isolation in silicon carbide devices

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Niskayuna, NY, United States of America

Alexander Viktorovich Bolotnikov