International Business Machines Corporation

Globalfoundries Inc.

Elpis Technologies Inc.

Samsung Electronics Co., Ltd.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Globalfoundries U.S. Inc.

Renesas Electronics Corporation

International Business Corporation

Globalfoundries U.S. 2 LLC

Matheson Tri-gas, Inc.

Adeia Semiconductor Solutions LLC

Alexander Reznicek

Pouya Hashemi

Kangguo Cheng

Ali Khakifirooz

Karthik Balakrishnan

Bruce Bennett Doris

Takashi Ando

Ruilong Xie

Bahman Hekmatshoartabari

Jingyun Zhang

Oscar Van Der Straten

Choonghyun Lee

Praneet Adusumilli

Thomas N Adam

Shogo Mochizuki

Tak H Ning

Veeraraghavan S Basker

Dominic Joseph Schepis

Keith E Fogel

Oleg Gluschenkov

Devendra K Sadana

Xin Miao

Stephen W Bedell

Pranita Kerber

Chih-Chao Yang

Jeng-Bang Yau

Soon-Cheon Seo

Qiqing Christine Ouyang

Junli Wang

Hemanth Jagannathan

Ghavam G Shahidi

Injo Ok

Nicolas J Loubet

Joshua M Rubin

Heng Wu

Joel Pereira De Souza

Sanjay C Mehta

Tenko Yamashita

Kern Rim

John Albrecht Ott

Min Yang

Judson Robert Holt

Hong He

Chen Zhang

Kevin K Chan

Meikei Ieong

Julien Frougier

Koichi Motoyama

Balasubramanian Pranatharthiharan

Guy M Cohen

Sivananda K Kanakasabapathy

Katherine Lynn Saenger

Dechao Guo

Michael A Guillorn

Michael Rizzolo

Jeffrey W Sleight

Isaac Lauer

Juntao Li

Jeremy R Fox

Effendi Leobandung

Martin G Keen

Chanro Park

Ramachandra Divakaruni

Ali Afzali-Ardakani

Davood Shahrjerdi

Paul Michael Solomon

Martin Michael Frank

Reinaldo Ariel Vega

Chandrasekharan Kothandaraman

Marc Adam Bergendahl

Tao Li

Tze-Chiang Chen

Vamsi Krishna Paruchuri

Balasubramanian S Haran

Carl John Radens

Shom Ponoth

Son Van Nguyen

Qizhi Liu

Jeehwan Kim

Xiuyu Cai

Zuoguang Liu

Chung-Hsun Lin

Andrew Mark Greene

Cheng-Wei Cheng

Chi-Chun Liu

Renee Tong Mo

Pranita Kulkarni

Sufi Zafar

David Louis Harame

Brent A Anderson

Theodorus E Standaert

Chun-chen Yeh

Keith Kwong Hon Wong

Fei Liu

Jack Oon Chu

Su Chen Fan

Kisik Choi

Eduard Albert Cartier

Ravi Nair

Evgeni Petrovich Gousev

A CFET (complementary field effect transistor) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, a first source/drain contact for the first source/drain region, and a second source drain contact for the second source drain region. The first source/drain contact is isolated from the second source/drain contact by an L-shaped isolation element including vertical and horizontal isolation elements.

Stacked complementary field effect transistors

A sensor device includes a vertically stacked cascode bipolar junction transistor pair, and a first trench having a first sidewall, wherein a portion of the first sidewall is provided by the first sensing surface, wherein a bipolar junction transistor and a dual-base bipolar junction transistor of the cascode bipolar junction transistor pair are stacked vertically along the first trench.

Vertically stacked cascode bipolar junction transistor (BJT) pair sensor

Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first pair of field effect transistors (FETs). Additionally, the semiconductor structure includes a second pair of FETs. Further, the semiconductor structure includes a shallow gate cut that separates a first pair of gates, a first pair of channels, and a first pair of source/drain (S/D) epitaxies of the first pair of FETs. Additionally, the first pair of S/D epitaxies are wired to a backside power rail (BPR) by a backside contact. Further, the semiconductor structure includes a deep gate cut that separates a second pair of S/D epitaxies of the second pair of FETs. Additionally, one of the second pair of S/D epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact. Further, another of the second pair of S/D epitaxies is wired to the BPR by a backside contact.

Forksheet transistor with dual depth late cell boundary cut

A semiconductor structure includes a backside power rail disposed in a backside dielectric layer, and dielectric spacer layers laterally extending inwardly from opposing sidewalls of the backside dielectric layer and on a portion of a bottom surface of the backside power rail.

Power distribution network with backside power rail

A semiconductor tunnel FET (field effect transistor) including a plurality of nanosheet channels disposed between a first source/drain region and a second source/drain region. The first source/drain region includes a p-type material; and the second source/drain region includes an n-type material.

Tunnel field effect transistor devices

A hybrid stacked semiconductor device includes a nanosheet stack on a substrate and an all-around gate. The nanosheet stack includes a first stack portion and a second stack portion. The first stack portion includes first channels. The second stack portion is stacked on the first stack portion, and includes second channels. The all-around gate includes a first gate portion that wraps around the first channels and a second gate portion that wraps around the second channels. A first gate extension contacts the first gate portion and the second gate extension contacts the second gate portion. At least one gate contact contacts the first gate extension to establish conductivity with the first gate portion and contacts the second gate extension to establish conductivity with the second gate portion.

Hybrid stacked field effect transistors

A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Gate induced drain leakage reduction in FinFETs

A memory device including a pedestal structure containing a cobalt aluminum layer and a magnesium-aluminum-oxide containing base layer both of which have a (001) crystal orientation is provided. The memory device further includes a magnetic tunnel junction (MTJ) pillar containing an ordered alloy forming an interface with the cobalt aluminum alloy layer. The use of the structural and textural engineered pedestal structure provides improved control of resistance, as well as improved magnetic properties such as higher tunnel magnetoresistance (TMR) and higher perpendicular magnetic anisotropy (PMA), and closer distribution of the ordered alloy.

Textured cobalt aluminum/magnesium-aluminum-oxide pedestal for memory devices

Embodiments are disclosed for a method for fabricating a semiconductor device. The method includes forming a recess under a region for a source/drain (S/D). The method further includes depositing a sacrificial placeholder liner conformally. Additionally, the method includes performing a sacrificial material overfill. Further, the method includes performing an etch back of the sacrificial material overfill. Also, the method includes performing S/D epitaxial (epi) growth over a remaining placeholder sacrificial liner to generate an S/D epi for the S/D.

Semiconductor device with void under source/drain region for backside contact

A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source/drain.

Epi growth uniformity with source/drain placeholder

A semiconductor device includes: a vertical transport field-effect transistor (VTFET) device including a bottom source/drain (S/D) epitaxial layer, a vertical fin channel formed on the bottom S/D epitaxial layer, and a top S/D epitaxial layer formed on the vertical fin channel. The bottom S/D epitaxial layer has an asymmetric profile in cross-section where a first side of the vertical fin channel is aligned with a first side of the bottom S/D epitaxial layer, and the bottom S/D epitaxial layer has a stepped profile that extends beyond a second edge of the vertical fin channel.

VTFET with controlled fin height

A method including forming a plurality of nanosheets on a substrate and forming a plurality of sacrificial layers on the substrate, wherein the plurality of nanosheets and the plurality of sacrificial layers are arranged as alternating layers. Forming and patterning a first hardmask located on top of one of the sacrificial layers and forming a second hardmask around the first hardmask. Patterning the plurality of nanosheets and the plurality of sacrificial layers. Forming and patterning a dummy gate located on top of first hard mask. Removing the plurality of sacrificial layers. Forming a plurality of nanowires, where the plurality of nanowires is formed by the removal of the plurality of sacrificial layers, where the removal of the plurality of sacrificial layers thins sections of each of the plurality of nanowires forming the plurality of nanowires.

Nanowire source/drain formation for nanosheet device

Embodiments are for vertical field effect transistors having different threshold voltages along the channel. A vertical fin having a vertical channel is formed, one end of the vertical channel including a doped layer, the doped layer causing a threshold voltage at the one end to be different from a remainder of the vertical channel. A source and a drain are formed each coupled to opposite ends of the vertical fin, gate material being formed on the vertical channel.

Vertical transport field effect transistors having different threshold voltages along the channel

A memory structure comprises a ReRAM module embedded in a substrate. An insulative layer is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area. A second electrode is located on the insulative layer. The second electrode is proximately connected to a second end of the ReRAM module. The second electrode comprises a second surface area, a plasma-interacting component, and a resistive component. The resistive component is located between the plasma-interacting component and the ReRAM module. A ratio of the first surface area to the second surface area creates a voltage between the first electrode and second electrode when the first surface area and second surfaces area are exposed to an application of plasma. The voltage forms a conductive filament in the ReRAM module.

Antenna assisted ReRAM formation

A field effect device is provided. The field effect device includes a semiconductor nanosheet segment above a substrate, and a T-shaped inner spacer on the semiconductor nanosheet segment. The field effect device further includes a gate dielectric layer on the semiconductor nanosheet segment, and a first work function material plug on the gate dielectric layer. The field effect device further includes a second work function material layer on the first work function material plug and a center portion of the gate dielectric layer, wherein the second work function material layer is a different work function material from the first work function material plug.

Nanosheet device with T-shaped dual inner spacer

Growing community of inventors

Troy, NY, United States of America

Alexander Reznicek