International Business Machines Corporation

Globalfoundries Inc.

Elpis Technologies Inc.

Samsung Electronics Co., Ltd.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Globalfoundries U.S. Inc.

Renesas Electronics Corporation

International Business Corporation

Globalfoundries U.S. 2 LLC

Matheson Tri-gas, Inc.

Adeia Semiconductor Solutions LLC

Alexander Reznicek

Pouya Hashemi

Kangguo Cheng

Ali Khakifirooz

Karthik Balakrishnan

Bruce Bennett Doris

Takashi Ando

Bahman Hekmatshoartabari

Ruilong Xie

Jingyun Zhang

Oscar Van Der Straten

Choonghyun Lee

Praneet Adusumilli

Thomas N Adam

Shogo Mochizuki

Tak H Ning

Veeraraghavan S Basker

Dominic Joseph Schepis

Keith E Fogel

Oleg Gluschenkov

Devendra K Sadana

Xin Miao

Stephen W Bedell

Pranita Kerber

Chih-Chao Yang

Jeng-Bang Yau

Soon-Cheon Seo

Qiqing Christine Ouyang

Junli Wang

Hemanth Jagannathan

Ghavam G Shahidi

Injo Ok

Nicolas J Loubet

Joshua M Rubin

Heng Wu

Joel Pereira De Souza

Sanjay C Mehta

Tenko Yamashita

Kern Rim

John Albrecht Ott

Min Yang

Judson Robert Holt

Hong He

Chen Zhang

Kevin K Chan

Meikei Ieong

Balasubramanian Pranatharthiharan

Julien Frougier

Koichi Motoyama

Guy M Cohen

Sivananda K Kanakasabapathy

Katherine Lynn Saenger

Dechao Guo

Michael A Guillorn

Michael Rizzolo

Jeffrey W Sleight

Isaac Lauer

Juntao Li

Jeremy R Fox

Effendi Leobandung

Martin G Keen

Chanro Park

Ramachandra Divakaruni

Ali Afzali-Ardakani

Davood Shahrjerdi

Paul Michael Solomon

Martin Michael Frank

Reinaldo Ariel Vega

Chandrasekharan Kothandaraman

Marc Adam Bergendahl

Tao Li

Tze-Chiang Chen

Vamsi Krishna Paruchuri

Balasubramanian S Haran

Carl John Radens

Shom Ponoth

Son Van Nguyen

Qizhi Liu

Jeehwan Kim

Xiuyu Cai

Zuoguang Liu

Chung-Hsun Lin

Andrew Mark Greene

Cheng-Wei Cheng

Chi-Chun Liu

Renee Tong Mo

Pranita Kulkarni

Sufi Zafar

David Louis Harame

Brent A Anderson

Theodorus E Standaert

Chun-chen Yeh

Keith Kwong Hon Wong

Fei Liu

Jack Oon Chu

Su Chen Fan

Eduard Albert Cartier

Kisik Choi

Ravi Nair

Evgeni Petrovich Gousev

Embodiments are for vertical field effect transistors having different threshold voltages along the channel. A vertical fin having a vertical channel is formed, one end of the vertical channel including a doped layer, the doped layer causing a threshold voltage at the one end to be different from a remainder of the vertical channel. A source and a drain are formed each coupled to opposite ends of the vertical fin, gate material being formed on the vertical channel.

Vertical transport field effect transistors having different threshold voltages along the channel

A memory structure comprises a ReRAM module embedded in a substrate. An insulative layer is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area. A second electrode is located on the insulative layer. The second electrode is proximately connected to a second end of the ReRAM module. The second electrode comprises a second surface area, a plasma-interacting component, and a resistive component. The resistive component is located between the plasma-interacting component and the ReRAM module. A ratio of the first surface area to the second surface area creates a voltage between the first electrode and second electrode when the first surface area and second surfaces area are exposed to an application of plasma. The voltage forms a conductive filament in the ReRAM module.

Antenna assisted ReRAM formation

A field effect device is provided. The field effect device includes a semiconductor nanosheet segment above a substrate, and a T-shaped inner spacer on the semiconductor nanosheet segment. The field effect device further includes a gate dielectric layer on the semiconductor nanosheet segment, and a first work function material plug on the gate dielectric layer. The field effect device further includes a second work function material layer on the first work function material plug and a center portion of the gate dielectric layer, wherein the second work function material layer is a different work function material from the first work function material plug.

Nanosheet device with T-shaped dual inner spacer

A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. Wherein the widths Wand Ware different from each other and the lengths Land Lare different from each other and wherein the substrate includes a tapered surface in the Y-direction.

Gate-all-around nanosheet-FET with variable channel geometries for performance optimization

Embodiments of the present invention include a phase change memory (PCM) array. The PCM array may include a plurality of PCM cells. Each PCM cell in the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a global heater surrounding the plurality of PCM cells having a thermally conductive material contacting each of the plurality of PCM cells. The global heater may be configured to receive an electric signal to heat the plurality of PCM cells simultaneously.

Global heater for phase change memory

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

Reactive serial resistance reduction for magnetoresistive random-access memory devices

A semiconductor device includes a PCM stack that includes bottom electrode liner over a lower heater. The bottom electrode liner has a top-down view plus (+) geometry with a 'horizontal' portion being orthogonal to a ‘vertical’ portion. An airgap is formed within the PCM stack in an area located adjacent and between the ‘horizontal’ portion and the ‘vertical’ portion. The airgap has a substantially smaller dielectric constant than the surrounding PCM stack material(s). Therefore, the airgap may effectively reduce the amount of current that leaks from the PCM stack when flowing from the bottom electrode liner to a top contact or top electrode. Further, the airgap may allow for expansion of the surrounding PCM stack material(s) that may result from the heating of the PCM stack.

Phase change memory programming current leakage reduction

A stacked field effect transistor (stacked-FET) device includes a first layer comprising at least one first layer transistor structure comprising a plurality of first layer terminals, a diffusion break dielectric fill region adjacent to one of the first layer terminals, a second layer overlying and adjacent to the first layer and comprising at least one second layer transistor structure comprising a plurality of second layer terminals, and a contact wiring between the first layer and the second layer passing through the diffusion break dielectric fill region of the first layer and connecting with one of the second layer terminals.

Diffusion-break region in stacked-FET integrated circuit device

A semiconductor device is provided that includes a local passthrough interconnect structure present in a non-active device region of the device. A dielectric fill material structure is located between the local passthrough interconnect structure and a functional gate structure that is present in an active device region that is laterally adjacent to the non-active device region. The semiconductor device has reduced capacitance (and thus circuit speed is not compromised) as compared to an equivalent device in which a metal-containing sacrificial gate structure is used instead of the dielectric fill material structure.

Reduced parasitic capacitance semiconductor device containing at least one local interconnect passthrough structure

Arrays of PCM devices and techniques for fabrication thereof having an integrated resistor formed during heater patterning for uniform voltage drop amongst the PCM devices are provided. In one aspect, a PCM device includes: at least one PCM cell including a phase change material disposed on a heater; and at least one resistor in series with the at least one PCM cell, wherein the at least one resistor includes a same combination of materials as the heater. A memory array and a method of forming a PCM device are also provided.

Uniform voltage drop in arrays of memory devices

A PCM cell includes a first electrode, a heater/PCM portion electrically connected to first electrode, the heater/PCM portion comprising a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding the projection liner. The stack includes a plurality of first layers comprised of a first material and having a plurality of first inner sides facing towards the projection liner, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers comprised of a second material that is different from the first material, and the second plurality of layers having a plurality of second inner sides facing towards the projection liner. The plurality of second inner sides that are offset from the plurality of first inner sides forming a plurality of gaps.

Phase change memory gaps

Embodiments of the invention are directed to a computer-implemented method that includes accessing, using a processor system, a three-dimensional (3D) model of a device-under-design (DUD). The processor system is used to receive a first design operation associated with the 3D model of the DUD. A collaboration dependency model is used to make a prediction of a dependency relationship between the first design operation and a second design operation.

Virtual reality design navigation using a temporal collaboration dependency map

A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.

Buried power rail formation for vertical field effect transistors

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a first set of nanosheets and a second set of nanosheets on top of the first set of nanosheets, wherein the first set of nanosheets has an uppermost nanosheet and the second set of nanosheets has a lowermost nanosheet, the lowermost nanosheet being separated from the uppermost nanosheet by a first gap; forming a conformal liner covering the first set of nanosheets and the first gap; covering a first portion of the conformal liner at the first gap with a protective stud; selectively removing a second portion of the conformal liner from end surfaces of the first set of nanosheets; and forming source/drain at the end surfaces of the first set of nanosheets. A structure formed thereby is also provided.

Source/drain epitaxy process in stacked FET

A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

Multi-Vt nanosheet devices

Growing community of inventors

Troy, NY, United States of America

Alexander Reznicek