International Business Machines Corporation

Infineon Technologies Ag

United Microelectronics Corp.

Infineon Technologies North America Corp.

United Microelectronics Co.

United Mircroelectronics Co.

Alexander M Hirsch

Robert C Wong

Pak Leung

Ernst H Demm

A semiconductor interconnect architecture provides a reduction in the intersection of vias on the last layer ('VL') and holes in the last thin metal layer ('MLHOLE') without degradation of the product yield or robustness, or increases copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Generation of metal holes by via mutation

A reduction in the intersection of vias on the last layer ('VL') and holes in the last thin metal layer ('MLHOLE') can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Method of producing a semiconductor interconnect architecture including generation of metal holes by via mutation

Growing community of inventors

Munich, Germany

Alexander M Hirsch