Pmc-sierra, Inc.

Alexander John Cochran

Larrie Simon Carr

Patrick Neil Bailey

A desired FIFO buffer fill level is continuously derived during mapping or demapping of plesiosynchronous data signals into synchronized data signals, or vice-versa. One of j predefined integer values Iis repetitively consecutively produced during each consecutive one of j FIFO buffer write clock cycles, where i=1, . . . , j and where j and the integer values Iare selected such that closely approximates the number of bits read from the FIFO buffer per FIFO buffer write clock cycle. During each kconsecutive FIFO buffer write clock cycle, a Bits_Read value I+Iis produced where k=1, . . . , p; a Bits_Written value is produced; a Gap_Pattern value is derived by subtracting the Bits_Read value from the Bits_Written value; and, the Gap_Pattern is added to a predefined value representative a FIFO buffer center fill level to produce the desired FIFO buffer fill level.

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Vancouver, Canada

Alexander John Cochran