Infineon Technologies Ag

Infineon Technologies Austria Ag

Continental Automotive Gmbh

Continental Automotive Technologies Gmbh

Alexander Heinrich

Konrad Roesl

Oliver Eichinger

Ralf Otremba

Edmund Riedl

Catharina Wille

Evelyn Napetschnig

Thorsten Meyer

Joachim Mahler

Gerald Ofner

Alexander Roth

Peter Scherl

Thomas Behrens

Tobias Schmidt

Wu Hu Li

Werner Josef Reiss

Michael Juerss

Kok Chai Goh

Horst Theuss

Ivan Nikitin

Thorsten Scharf

Bernhard Weidgans

Stefan Hermann

Stephan Bradl

Arthur Unrau

Stefan Miethaner

Kirill Trunov

Hannes Eder

Manfred Mengel

Manfred Schneegans

Thomas Fischer

Gunther Mackh

Stefan Landau

Ulrich Emmerling

Markus Menath

Paul Frank

Daniel Pedone

Katharina Umminger

Ulrike Fastner

Franz Plattner

Reinhard Hess

Lim Fong

Christina Yeong

Annette Hebling

Alexandra Ludsteck-Pechloff

Gabriel Maier

Steffen Orso

Petteri Palm

Khalil Hosseini

Klaus Schiess

Martin Gruber

Hans-Joerg Timme

Irmgard Escher-Poeppel

Bernd Goller

Peter Strobel

Frank Daeche

Karsten Guth

Ralf Wombacher

Franco Mariani

Holger Torwesten

Steffen Jordan

Magdalena Hoier

Bernd Rakow

Rupert Fischer

Ivan Galesic

Stefan Schwab

Andreas Munding

Richard Knipper

Franz Heininger

Georg Käufl

Jens Goerlich

Christine Igl

Steffan Jordan

Tobias Simbeck

Konrad Rösl

A method of producing a semiconductor device includes providing a semiconductor die, providing a metal joining partner, forming a diffusion solderable region by an inkjet metal printing process, forming an assembly to include the diffusion solderable region in between the metal joining partner and the semiconductor die, and performing a diffusion soldering process that forms a soldered joint from the diffusion solderable region in between the semiconductor die and the metal joining partner.

Inkjet printing of diffusion solder

A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin. Methods of forming the layer structure, a chip package and a chip arrangement are also described.

Method of forming an intermetallic phase layer with a plurality of nickel particles

A method for fabricating a semiconductor device includes providing a die with a metallization layer including a first metal with a high melting point; providing a die carrier including a second metal with a high melting point; providing a solder material including a third metal with a low melting point; providing a layer of a fourth metal with a high melting point on the semiconductor die or the die carrier; and soldering the semiconductor die to the die carrier and creating: a first intermetallic compound between the semiconductor die and the die carrier and including the first metal and the third metal; a second intermetallic compound between the first intermetallic compound and the die carrier and including the second metal and the third metal; and precipitates of a third intermetallic compound between the first intermetallic compound and the second intermetallic compound and including the third metal and the fourth metal.

Semiconductor device and method for fabricating a semiconductor device

An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

Electronic device with multi-layer contact and system

A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.

Semiconductor package and method for fabricating a semiconductor package

A semiconductor device includes: a semiconductor die having a metal region; a substrate having a metal region; and a soldered joint between the metal region of the semiconductor die and the metal region of the substrate. One or more intermetallic phases are present throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the semiconductor die and the metal region of the substrate. The soldered joint has the same length-to-width aspect ratio as the semiconductor die.

Semiconductor device having a soldered joint with one or more intermetallic phases

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

Pre-plating of solder layer on solderable elements for diffusion soldering

A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin.

Layer structure with an intermetallic phase layer and a chip package that includes the layer structure

A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.

Semiconductor device and method for fabricating the same

A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.

Method of forming a chip package and chip package

A semiconductor device includes a semiconductor die with a metallization layer including a first metal with a comparatively high melting point, a die carrier including a second metal with a comparatively high melting point, a first intermetallic compound arranged between the semiconductor die and the die carrier and including the first metal and a third metal with a comparatively low melting point, a second intermetallic compound arranged between the first intermetallic compound and the die carrier and including the second metal and the third metal, and precipitates of a third intermetallic compound arranged between the first intermetallic compound and the second intermetallic compound and including the third metal and a fourth metal with a comparatively high melting point.

A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

Semiconductor device including a solder compound containing a compound Sn/Sb

A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.

A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.

Flat lead package formation method

Growing community of inventors

Bad Abbach, Germany

Alexander Heinrich