Micron Technology Incorporated

Texas Instruments Corporation

Alessandro Torsi

Carlo Musilli

Durai Vishak Nirmal Ramaswamy

Akira Goda

Seiichi Aritome

Giulio Giuseppe Marotta

Tommaso Vali

Krishna Kumar Parat

Prashant S Damle

Noel Rocklein

Stefano Perugini

Kalpana Vakati

Murali Balakrishnan

Sanh D Tang

John K Zahurak

Mark Alan Helm

Doyle W Rivers

Xiaonan Chen

Giuliano Gennaro Imondi

Muralikrishnan Balakrishnan

Giuseppe Cautiero

Koteswara Rao Chintapalli

Giuseppe Miccoli

Felice Russo

Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing another pulse to the memory cell or otherwise stressing the cell. The another pulse may be of an opposite polarity to the set or reset pulses already applied. If the memory cell is no longer in the target state after providing the another pulse, additional set or reset pulses may be applied to achieve a stable state.

Apparatuses and methods for determining stability of a memory cell

A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.

Resistive memory elements, resistive memory cells, and resistive memory devices

Methods of forming resistive memory elements

Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.

Reducing read failure in a memory device

Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300&#xb0; C. to about 500&#xb0; C. for a time of from about 1 minute to about 1 hour.

Memory cells and methods of forming memory cells

Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.

Memory device having improved programming operation

Memory cells

Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

Voltage switching in a memory device

A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.

Reducing effects of erase disturb in a memory device

Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying a set of incrementing program pulses to program a selected cell to a first target threshold voltage, and applying a set of incrementing inhibit pulses to an unselected cell to fine-tune program the selected cell to a second threshold voltage.

Programming methods and memories

Growing community of inventors

Avezzano, Italy

Alessandro Torsi