Winbond Electronics Corporation

Information Storage Devices, Inc.

Windbond Electronics Corp.

Albert V Kordesch

Chun-Mai Liu

Ming-Bing Chang

James Brennan, Jr

Kung-Yen Su

Hieu Van Tran

Loc Bao Hoang

Peter J Holzmann

Lawrence D Engh

Len-Yi Leu

Sheng-Hsiung Hsueh

Anthony Dunne

Peter Holzmann

Ganshu Ben Lee

Geoff Jackson

Kai-Man Chan

Ken Su

Chun-Mail Liu

Ping Guo

A method of forming a semiconductor memory having rows and columns of memory cells is as follows; forming a plurality of rows of program gate lines from a second layer polysilicon; forming a plurality of rows of select gate lines from a third polysilicon layer; forming a plurality of rows of diffusion source lines: forming a plurality of local bitlines from a first layer metal, the cells along each column being divided into a pre-designated number of groups, and drains of the cells in each group being connected to a local bitline extending across the cells in the group of cells; and forming a plurality of global bitlines from a second layer metal extending along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Method of forming memory arrays based on a triple-polysilicon source-side injection non-volatile memory cell

Techniques to more accurately read values stored in data cells. In an aspect, one reference cell is provided for each group of data cells having similar configuration (e.g., similar layout and orientation). For split-gate memory cells arranged in pairs, each pair includes two data cells implemented as mirrored image of one another. Two reference cells may then be used, one reference cell for each data cell in a pair. In another aspect, the data paths for the reference and data cells for read operation are matched. This matching may be achieved by using the same circuit design for the data and reference sense amplifiers, using the same layout and orientation for the sense amplifiers, matching the lines for the two data paths, matching the structure (e.g., length and width) and the diffusion region (e.g., doping concentration and contact) for the sense amplifiers and lines, and so on.

Dual reference cell for split-gate nonvolatile semiconductor memory

A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells. The floating gate of each cell is from a first layer polysilicon, the program gate lines are from a second polysilicon layer, the select gate lines are from a third polysilicon layer, and the source lines are diffusion lines.

Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell

A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.

Method of making triple self-aligned split-gate non-volatile memory device

A method of forming a capacitor on a substrate includes forming a first polysilicon layer overlying the substrate to define a floating gate. A second polysilicon overlying the first polysilicon layer is formed to define a control gate and a first electrode of the capacitor. A dielectric layer is formed over the second polysilicon layer. A third polysilicon layer is formed over the dielectric layer. The third polysilicon layer is etched to define a second electrode of the capacitor. Thereafter the dielectric layer is etched.

Capacitor fabrication process for analog flash memory devices

Adaptive programming method and apparatus for flash memory analog storage. The present invention method is to adjust the voltage of the programming pulse each time based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse. The algorithm is &ldquo;adaptive&rdquo; because the voltage of each pulse is adapted to whatever the cell needs. If the cell is programming too slowly, the voltage is increased dramatically to make it faster. Conversely if the results show that a particular cell is programming too fast, the next voltage pulse is increased by only a small amount (or even decreased if necessary). Because the response of the cell is non-linear, a special analog circuit is used to calculate the optimum voltage for each pulse. As one alternative, a digital calculation may also be used to program the cells. Because of the programming speed of the exemplary method, a voice signal may be sampled and stored in flash memory one cell at a time. Variable programming parameters other than voltage may be used if desired.

Adaptive programming method and apparatus for flash memory analog storage

The present invention is a method and apparatus to program a flash memory cell in an analog storage array. A read circuit reads a cell voltage of a flash memory cell. A comparator compares the read cell voltage with an input voltage representing an analog signal. The comparator generates first and second comparison results. A programming circuit generates a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result. The programming circuit generates a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.

Programming flash memory analog storage using coarse-and-fine sequence

An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ('SPI') that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes row and column redundancy to increase production yield.

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San Jose, CA, United States of America

Albert V Kordesch