National Yang Ming Chiao Tung University

Taiwan Semiconductor Manufacturing Comp. Ltd.

Albert Chin

Tong-Chern Ong

Ming-Tsong Wang

Kuo-Tai Huang

Chun-Yang Tsai

Kang-Cheng Lin

Donald Y Chao

San-Yuan Chen

Fong-Yu Yen

Ping-Fang Hung

Chun-Hu Cheng

Hsueh-Jen Yang

Chun-Hung Lai

Chia-Liang Sun

A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1 V 10-year extrapolated retention window at 125&#xb0; C. and excellent 10endurance at a fast 100 &#x3bc;s and &#xb1;16 V program/erase. This is achieved using As-implanted higher &#x3ba; trapping layer with deep 5.1 eV work-function of As. In contrast, the un-implanted device only has a small 10-year retention window of 1.9 V at 125&#xb0; C. A MoN&#x2014;[SiO&#x2014;LaAlO]&#x2014;[Ge&#x2014;HfON]&#x2014;[LaAlO&#x2014;SiO]&#x2014;Si CTF device is also provided with record-thinnest 2.5-nm Equivalent-SiN-Thickness (ENT) trapping layer, large 4.4 V initial memory window, 3.2 V 10-year extrapolated retention window at 125&#xb0; C., and 3.6 V endurance window at 10cycles, under very fast 100 &#x3bc;s and low &#xb1;16 V program/erase. These were achieved using Ge reaction with HfON trapping layer for better charge-trapping and retention.

Flash memory

Resistive random access memory (RRAM) using stacked dielectrics and a method for manufacturing the same are disclosed, where a setting power of only 4 &#x3bc;W, an ultra-low reset power of 2 nW, good switching uniformity and excellent cycling endurance up to 5&#xd7;10cycles were achieved simultaneously. Such record high performances were reached in a Ni/GeO/nano-crystal-TiO/TaON/TaN RRAM device, where the excellent endurance is 4&#x2dc;6 orders of magnitude larger than existing Flash memory. The very long endurance and low switching energy RRAM is not only satisfactory for portable SSD in a computer, but may also create new applications such as being used for a Data Center to replace high power consumption hard discs.

Resistive random access memory (RRAM) using stacked dielectrics and method for manufacturing the same

A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.

Flash memory cells having leakage-inhibition layers

A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device.

Metal gates of PMOS devices having high work functions

This invention proposes a method for making very low threshold voltage (V) metal-gate/high-&#x3ba; CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vof +0.05 and 0.03 V, high mobility of 90 and 243 cm/Vs, and small 85&#xb0; C. bias-temperature-instability &#x3c;32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.

[object Object]

A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably has a conduction band lower than a conduction band of silicon. The blocking layer is preferably formed of a high-k dielectric material.

Flash memory with deep quantum well and high-K dielectric

The present invention relates to a method for manufacturing a ferroelectric field-effect transistor, particularly to a ferroelectric field-effect transistor with a metal/ferroelectric/insulator/semiconductor (MFIS) gate capacitor structure. The method comprises steps of depositing a bismuth layered ferroelectric film on the insulator buffered Si, after a high-temperature thermal treatment, depositing an upper electrode on the bismuth layered ferroelectric film.

Growing community of inventors

Hsinchu, Taiwan

Albert Chin