Tokyo Electron Limited

Other

Tokyo Electron Limi Ted

Tokyo Eelctron Limited

Akiteru Ko

Angelique Denise Raley

Eric Chih-Fang Liu

Toshiharu Wada

Kaoru Maekawa

Vinh Hoang Luong

Alok Ranjan

Nihar Mohanty

Yuki Kikuchi

David L O'Meara

Kiyohito Ito

Christopher Cole

Satoru Nakamura

Anton J deVillers

Lee Chen

Kaushik Arun Kumar

Subhadeep Kal

Takashi Enomoto

Masaaki Hagihara

Hamed Hajibabaeinajafabadi

Hiroyuki Takahashi

Chi-Chun Liu

Kandabara N Tapily

Gerrit J Leusink

Anthony Dip

Sergey Alexandrovich Voronin

Hongyu Henry Yue

Vidhya Chakrapani

Richard Farrell

Asao Yamashita

Daniel Joseph Prager

Hiroyuki Toshima

Soo Doo Chae

Jodi Grzeskowiak

Masafumi Urakawa

Shan Hu

Yu-Hao Tsai

Kosuke Ogasawara

Vinayak Rastogi

Henan Zhang

Kazuya Okubo

Hiromasa Mochiki

Arthur H Laflamme, Jr

Scott W Lefevre

Masayuki Sawataishi

Hirokazu Aizawa

Sophie Thibaut

Fumihiko Higuchi

Elliott Franke

Nobuhiro Iwama

Hiromitsu Kambara

Vaidya Bharadwaj

Edward Heller

Annie Xia

Wan Jae Park

Shinji Hamamoto

Chia-Yun Hsieh

Hiromitsu Tokyo Electron US Holdings Inc Kambara

A method for processing a substrate includes forming a metal oxide resist over the substrate, exposing the metal oxide resist to an extreme ultraviolet light pattern, and flowing a selective gas over the metal oxide resist. The selective gas increases a selectivity of the exposed metal oxide resist to a developing gas. The method further includes flowing the developing gas over the metal oxide resist in a processing chamber and etching the substrate using remaining portions of the metal oxide resist as a mask.

Metal oxide resists for EUV patterning and methods for developing the same

A method of processing a substrate includes receiving a substrate including a photoresist film including exposed and unexposed portions, etching parts of the unexposed portions of the photoresist film with a developing gas in a process chamber to leave a residual part of the unexposed portions, and purging the developing gas from the process chamber with a purging gas. After purging the developing gas, the residual part of the unexposed portions is etched with the developing gas. The substrate is etched using exposed portions of the photoresist film as a mask.

Cyclic method for reactive development of photoresists

A method of processing a substrate that includes receiving a patterned photoresist formed over a substrate, the patterned photoresist defining initial openings, each of the initial openings including a first side and an opposite second side along a first direction; depositing a mask material preferentially on the first side within the initial openings using an oblique deposition process performed at a first angle inclined from the first side; and removing a portion of the patterned photoresist using an oblique etch process performed at a second angle inclined from the second side, the mask material and a remaining portion of the patterned photoresist defining final openings.

Oblique deposition and etch processes

A method of forming a device includes forming a hard mask layer over an underlying layer of a substrate, forming an anti-reflective coating layer over the hard mask layer, forming a patterned resist layer over the anti-reflective coating layer, and forming a mandrel including the anti-reflective coating layer by patterning the anti-reflective coating layer using the patterned resist layer as an etch mask. The method includes forming a sidewall spacer on the mandrel including the anti-reflective coating layer, forming a freestanding spacer on the hard mask layer by removing the mandrel from the anti-reflective coating layer, and using the freestanding spacer as an etch mask, patterning the underlying layer of the substrate.

Method for pitch split patterning using sidewall image transfer

Embodiments are described herein that apply capping layers to cores prior to spacer formation in self-aligned multiple patterning (SAMP) processes to achieve vertical spacer profiles. For one embodiment, a plasma process is used to deposit a capping layer on cores, and this capping layer causes resulting core profiles to have protective caps. These protective caps formed with the additional capping layer help to reduce or minimize material loss and corner loss of the core material during spacer deposition and spacer etch processes. This reduction in core material loss improves the resulting spacer profile so that a more vertical profile is achieved. For one embodiment, an angle of 80-90 degrees is achieved for vertical sidewalls of the spacers adjacent core sites with respect to the horizontal surface of the underlying layer, such as a hard mask layer formed on a substrate for a microelectronic workpiece.

Method and system for capping of cores for self-aligned multiple patterning

Embodiments are disclosed for reducing substrate breaks which result from inadequate de-chucking. Contaminants are removed from the surface of a chuck by exposing the chuck to a plasma process that comprises a hydrogen (H)-containing plasma. The chuck is subjected to the hydrogen-based plasma when no substrate is on the chuck. In one embodiment, the plasma is a hydrocarbon-based plasma. Hydrogen in the hydrocarbon plasma may react with and remove the contaminants. The process may further include an additional plasma step for removal of any newly formed materials that may result from the hydrocarbon plasma. The removal step may be, for example, a subsequent plasma ash step. In one embodiment, the chuck is an electrostatic chuck and the contaminants comprise fluorine. By removing contaminants from the chuck surface, improved substrate de-chucking occurs. This improvement correspondingly leads to less substrate breakage when removing substrates from the chuck.

Surface fluorination remediation for aluminium oxide electrostatic chucks

Embodiments reduce or eliminate microbridge defects in extreme ultraviolet (EUV) patterning for microelectronic workpieces. A patterned layer is formed over a multilayer structure using an EUV patterning process. Protective material is then deposited over the patterned layer using one or more oblique deposition processes. One or more material bridges extending between line patterns within the patterned layer are then removed while using the protective material to protect the line patterns. As such, microbridge defects caused in prior solutions are reduced or eliminated. For one embodiment, the oblique deposition processes include physical vapor deposition (PVD) processes that apply the same or different protective materials in multiple directions with respect to line patterns within the patterned layer. For one embodiment, the removing includes one or more plasma trim processes. Variations can be implemented.

Methods to reduce microbridge defects in EUV patterning for microelectronic workpieces

Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.

Methods for EUV inverse patterning in processing of microelectronic workpieces

Embodiments are described herein to reshape spacer profiles to improve spacer uniformity and thereby improve etch uniformity during pattern transfer associated with self-aligned multiple-patterning (SAMP) processes. For disclosed embodiments, cores are formed on a material layer for a substrate of a microelectronic workpiece. A spacer material layer is then formed over the cores. Symmetric spacers are then formed adjacent the cores by reshaping the spacer material layer using one or more directional deposition processes to deposit additional spacer material and using one or more etch process steps. For one example embodiment, one or more oblique physical vapor deposition (PVD) processes are used to deposit the additional spacer material for the spacer profile reshaping. This reshaping of the spacer profiles allows for symmetric spacers to be formed thereby improving etch uniformity during subsequent pattern transfer processes.

Methods to reshape spacer profiles in self-aligned multiple patterning

A substrate is provided with a patterned layer, for example, a photo resist layer, which may exhibit line roughness. In one exemplary embodiment, the patterned layer may be an extreme ultraviolet (EUV) photo resist layer. In one method, selective deposition of additional material is provided on the EUV photo resist layer after patterning to provide improved roughness and lithographic structure height to allow for more process margin when transferring the pattern to a layer underlying the photo resist. The additional material is deposited selectively thicker in areas above the photo resist than in areas where the photo resist is not present, such as exposed areas between the photo resist pattern. Pattern transfer to a layer underlying the photo resist may then occur (for example via an etch) while the patterned photo resist and additional material above the photo resist may collectively operate as an etch mask.

Method of line roughness improvement by plasma selective deposition

A method includes providing a substrate including mandrels of a first material positioned on an underlying layer. Each of the mandrels includes a first sidewall and an opposing second sidewall. The method further includes forming sidewall spacers made of a second material and including a first sidewall spacer abutting each respective first sidewall and a second sidewall spacer abutting each respective second sidewall. The mandrels extend above top surfaces of the sidewall spacers. The method also includes forming first capped sidewall spacers by depositing a third material on the first sidewall spacers without depositing on the second sidewall spacers, forming second capped sidewall spacers by depositing a fourth material on the second sidewall spacers without depositing on the first sidewall spacers, and selectively removing at least one of the first material, the second material, the third material, and the fourth material to uncover an exposed portion of the underlying layer.

Substrate processing method using multiline patterning

In certain embodiments, a method of forming a semiconductor device includes forming a patterned resist layer over a hard mask layer using an extreme ultraviolet (EUV) lithography process. The hard mask layer is disposed over a substrate. The method includes patterning the hard mask layer using the patterned resist layer as an etch mask. The method includes smoothing the hard mask layer by forming, using a first atomic layer etch step, a first layer by converting a first portion of the hard mask layer, and by removing, using a second atomic layer etch step, the first layer.

Forming a semiconductor feature using atomic layer etch

A method of forming a device includes depositing a first etch mask layer over a mandrel formed using a lithography process. The method includes depositing a second etch mask layer over the first etch mask layer. The method includes, using a first anisotropic etching process, etching the first etch mask layer and the second etch mask layer to form an etch mask including the first etch mask layer and the second etch mask layer. The method includes removing the mandrel to expose an underlying surface of the layer to be patterned. The method includes, using the etch mask, forming a feature by performing a second anisotropic etching process to pattern the layer to be patterned, where during the first anisotropic etching process, the first etch mask layer etches at a first rate and the second etch mask layer etches at a second rate, and where the first rate is different from the second rate.

Multiple patterning processes

A self-aligned multiple patterning (SAMP) multi-color spacer patterning process is disclosed for formation of structures on substrates. Trenches and vias may be formed in the process. A trench memorization layer and a via memorization layer may be formed on the substrate. In one embodiment, the trench memorization layer and the via memorization layer are formed between the multi-color spacer patterning structures and a low-k interlayer dielectric layer. The use of the trench memorization layer and the via memorization layer allows the formation of trenches and vias in the low-k interlayer dielectric layer without causing damage to the low-k properties of the low-k interlayer dielectric layer.

Method and process using dual memorization layer for multi-color spacer patterning

A patterned photo resist layer (for example an EUV photo resist layer), which may exhibit line width roughness (LWR) and line edge roughness (LER) or scum is treated with a plasma treatment before subsequent etching processes. The plasma treatment reduces LWR, LER, and/or photo resist scum. In one exemplary embodiment, the plasma treatment may include a plasma formed using a gas having a boron and halogen compound. In one embodiment, the gas compound may be a boron and chlorine compound, for example boron trichloride (BCl) gas. In another embodiment, the gas compound may be a boron and fluorine compound, for example BFgases. The plasma treatment process may modify the photoresist surface to improve LWR, LER, and scum effects by removing roughness from the photo resist surface and removing photo resist residues which may case scumming.

Plasma treatment method to improve photo resist roughness and remove photo resist scum

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Schenectady, NY, United States of America

Akiteru Ko