Intel Corporation

Akira Kakizawa

Kevin M Connolly

James E Breisch

Jung S Kang

Berni W Landau

Mark A Beiley

Cory E Weber

Shaofeng Yu

Ronald W Swartz

Zong-Fu Li

Bharani Thiruvengadam

Joseph W Parks, Jr

Mamun Ur Rashid

Cass A Blodgett

Eric T Fought

Erik T Fought

Mark A Arellano

Carlos A Ortega

This disclosure relates generally to an electrical circuit and method. A capacitive element can be configured to be coupled in series with an electronic package component. A path resistance can be electrically coupled to the capacitive element. A driver can be configured to electrically charge the capacitive element. A voltage detector can be coupled to the capacitive element and configured to identify a condition of the electronic package component based on a measured voltage of the capacitive element.

Alternating current coupled electronic component test system and method

A method and an apparatus for testing transmitter and receiver have been disclosed. One embodiment of the apparatus includes a plurality of multiplexers to select one of a positive and a negative transmitter pins, and a first comparator to compare a voltage of the selected pin with a first reference voltage to determine whether there is leakage at the selected pin. Other embodiments are described and claimed.

Method and an apparatus for testing transmitter and receiver

A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.

Test circuit for delay lock loops

A method and an apparatus for testing transmitter and receiver have been disclosed. One embodiment of the apparatus includes a plurality of multiplexers to select one of a positive transmitter pin and a negative transmitter pin, and a first comparator to compare a voltage of the selected pin with a first reference voltage to determine whether leakage exists at the selected pin. Other embodiments are described and claimed.

A buffer circuit is provided having a driver device and an input device to receive a first set of signals and to produce a second set of signals. The driver device may receive the second set of signals and output a third set of signals based on the second set of signals input to said driver device. A comparing device may receive the third set of signals from the driver device and produce a fourth set of signals based on the third set of signals, the comparing device may compare the fourth set of signals with the first set of signals.

Method and apparatus for testing an I/O buffer

Hardware or software to test a circuit with a set of functional vectors. The invention compares expected results of functional vectors with the actual results of the test circuit. If there is a miscompare, a recursive comparison is done prior to the first clock cycle of the miscompare.

Method and apparatus for failure detection utilizing functional test vectors and scan mode

A stereoscopic image pair may be viewed through a plate having an appropriately-sized aperture. When the viewer's left and right eyes view the image pair through the aperture, a stereoscopic effect may result. In one embodiment, a stereoscopic video conference system may include stereoscopic cameras positioned between the viewer and the apertured plate.

Viewing stereoscopic image pairs

A technique for testing digital-to-analog converters includes providing a set of digital input signals to the digital-to-analog converters and comparing a resulting combined output signal from the digital-to-analog converters to a comparison value. A determination is made as to whether the resulting combined output signal is within a predetermined tolerance defined by the comparison value. An apparatus for testing digital-to-analog converters also is disclosed.

Testing of digital-to-analog converters

Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

Reduced leakage trench isolation

Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

Growing community of inventors

Phoenix, AZ, United States of America

Akira Kakizawa